LC86E7248 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LC86E7248 Datasheet PDF : 19 Pages
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Parameter
LCD output
regulation
Symbol
VODLS
Pins
S0 to S47
VODLC COM0 to COM3
LCD ladder
resistor
RLCD(1)
RLCD(2)
Pull-up MOS
Rpu
Tr. resistor
Hysteresis
voltage
VHIS
Pin capacitance CP
•Ports 0, 1, 3
•Ports A,B,C,D,E,F
•Ports 70, 71, 72, 73
•Port 1
•Ports 70, 71, 72, 73
• RES
All pins
LC86E7248
Conditions
•Deference voltage
to ideal value
•VLCD, 2/3VLCD,
1/3VLCD
•Deference voltage
to ideal value
•VLCD, 2/3VLCD,
1/2VLCD, 1/3VLCD
Resistance at a
ladder resistor
•Resistance at a
ladder resistor
•1/2R mode
VOH=0.9VDD
VDD[V] min.
4.5-6.0
0
Ratings
typ.
4.5-6.0
0
4.5-6.0
60
4.5-6.0
30
4.5-6.0
15
40
unit
max.
±0.2 V
±0.2
kΩ
70
Output disable
4.5-6.0
0.1VDD
V
•f=1MHz
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
4.5-6.0
10
pF
4. Serial Input / Output Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set up time
Data hold time
Output delay time
(Serial clock is
external clock)
Output delay time
(Serial clock is
internal clock)
Symbol
Pins
tCKCY(1) SCK0,
tCKL(1) SCK1
tCKH(1)
tCKCY(2) SCK0,
tCKL(2) SCK1
tCKH(2)
tICK
•SI0,SI1
•SB0,SB1
tCKI
tCKO(1)
•SO0, SO1
•SB0, SB1
tCKO(2)
Conditions
Refer to figure 5.
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Refer to figure 5.
•Data set-up to
SCK0, 1
•Data hold from
SCK0, 1
•Refer to figure 5.
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Data hold from
SCK0, 1
•Refer to figure 5.
Ratings
unit
VDD[V] min.
typ.
max.
4.5-6.0
2
tCYC
1
1
4.5-6.0
2
1/2
tCKCY
1/2
tCKCY
4.5-6.0 0.1
µs
4.5-6.0 0.1
4.5-6.0
7/12tCYC
+0.2
4.5-6.0
1/3tCYC
+0.2
No.6749-12/19
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