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LH5420P-25

256 × 36 × 2 Bidirectional FIFO

Sharp Electronics 

LH5420

256 × 36 × 2 Bidirectional FIFO

OPERATIONAL DESCRIPTION (cont’d)

HIGH, ACKA/B may be considered as a synchronous,

predictive boundary flag. That is, ACKA/B acts as a syn-

chronized predictor of the Almost-Full Flag AF for write

operations, or as a synchronized predictor of the Almost-

Empty Flag AE for read operations.

Outside the ‘almost-full’ region and the ‘almost-empty’

region, ACKA/B remains continuously HIGH whenever

REQA/B is held continuously HIGH. Within the ‘almost-full’

region or the ‘almost-empty’ region, ACKA/B occurs only

on every third cycle. Assuming that ACKA/B is being used

to control ENA/B, this repetition-rate decrease can help to

prevent an overrun of the FIFO’s actual full or empty

boundaries, and to ensure that the tFWL (first write latency)

and tFRL (first read latency) specifications are satisfied

before ACKA/B is received.

The ‘almost-full region’ is defined as ‘that region, where

the Almost-Full Flag is being asserted’; and the ‘almost-

empty region’ as ‘that region, where the Almost-Empty

Flag is being asserted.’ Thus, the extent of these ‘almost’

regions depends on how the system has programmed the

offset values for the Almost-Full Flags and the Almost-

Empty Flags. If the system has not programmed them,

then these offset values remain at their default values,

eight in each case.

If a write attempt is unsuccessful because the corre-

sponding FIFO is full, or if a read attempt is unsuccessful

because the corresponding FIFO is empty, ACKA/B is not

asserted in response to REQA/B.

If the REQ/ACK handshake is not used, then the

REQA/B input may be used as a second enable input, at

a possible minor loss in maximum operating speed. In this

case, the ACKA/B output may be ignored.

WARNING: Whether or not the REQ/ACK handshake is

being used, the REQA/B input for a port must be asserted

for the corresponding FIFO to operate.

Data Retransmit

A retransmit operation resets the read-address pointer

of the corresponding FIFO (#1 or #2) back to the first FIFO

physical memory location, so that data may be reread.

The write pointer is not affected. The status flags are

updated; and a block of up to 256 data words, which

previously had been written into and read from a FIFO,

can be retrieved. The block to be retransmitted is bounded

by the first FIFO memory location, and the FIFO memory

location addressed by the write pointer. FIFO #1 retrans-

mit is initiated by strobing the RT1 pin LOW. FIFO #2

retransmit is initiated by strobing the RT2 pin LOW. Read

and write operations to a FIFO should be stopped while the

corresponding Retransmit signal is being asserted.

Parity Check

The Parity Check Flags, PFA and PFB, are asserted

(LOW) whenever there is a parity error in the data word

present on the Port A data bus or the Port B data bus

respectively. The inputs to the parity-evaluation logic

come directly (via isolation transistors) from the data-bus

bonding pads, in each case.

The four bytes of a 36-bit data word are grouped as

D0 – D8, D9 – D17, D18 – D26, and D27 – D35. The parity of

each nine-bit byte is individually checked, and the four single-

bit parity indications are logically inclusive-ORed to produce

the Parity-Flag output. Parity checking is initialized for odd

parity at reset, but can be reprogrammed for even parity or for

odd parity during operation. Control-Register bit 0 (zero)

selects the parity mode, odd or even (see Table 3).

All nine bits of each byte are treated alike by the parity

logic. The byte parity over the nine bits is compared with

the Parity Mode bit in the Control Register, to generate a

byte-parity-error indication. Then, the four byte-parity-

error signals are NORed together, to compute the asser-

tive-LOW parity-flag value.

Word-Width Selection on Port B

The word width of data access on Port B is selected

by the WS0 and WS1 control inputs. WS0 and WS1 both

are tied HIGH for 36-bit access; they both are tied LOW

for single-byte access. For double-byte access, WS0 is

tied HIGH and WS1 is tied LOW.

In the single-byte-access or double-byte-access

modes, FIFO write operations on Port B essentially pack

the data to form 36-bit words, as viewed from Port A.

Similarly, single-byte or double-byte FIFO read opera-

tions on Port B essentially unpack 36-bit words through a

series of shift operations. FIFO status flags are updated

following the last access which forms a complete 36-bit

transfer.

Since the values for each status flag are computed by

logic directly associated with one of the FIFO-memory

arrays, and not by logic associated with Port B, the flag

values reflect the array fullness situation in terms of com-

plete 36-bit words, and not in terms of bytes or double bytes.

However, there is no suchrestriction for switching from

writing to reading, or from reading to writing, at Port B. As

long as tRWS, tDS, and tA are satisfied, R/WB may change

state after any single-byte or double-byte access, and not

only after a full 36-bit-word access.

Also, the word-width-writing feature continues to oper-

ate properly in ‘loopback’ mode.

Note that the programmable word-width-matching

feature is only supported for FIFO accesses. Mailbox and

Data Bypass operations do not support word-width

matching between Port A and Port B. Tables 2, 3, and 4,

and Figures 4a and 4b summarize word-width selection

for Port B.

Table 2. Port B Word-Width Selection

WS1

WS0

PORT B DATA WIDTH

H

H

36-Bit

H

L

(Reserved)

L

H

18-Bit

L

L

9-Bit

6-218

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