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S6B2104 데이터 시트보기 (PDF) - Samsung

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S6B2104 Datasheet PDF : 12 Pages
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S6B2104
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION
Table 1. Pin Description
Pin No I/O
Name
Function
VDD (40) Power Operating voltage For logical circuit (+5V ± 10%, +3V ± 10%)
VSS (42)
0V (GND)
VEE (33)
Negative supply
voltage
For LCD drive circuit
V1, V3, V4 I LCD driver output Bias supply voltage terminals to drive the LCD.
(34-36)
voltage level
Bias voltage divided by the resistance is usually used
as supply voltage source. (refer to note 1)
S1-S80
(1-30,
51-100)
O LCD driver output Display data output pin which corresponds to the
respective latch contents. One of V1, V3, V4 and VEE
is selected as a display driving voltage source
according to the combination of the latched data level
and M signal (refer to note 2)
CL2 (47)
I Data shift clock
Clock pulse input for the 4 bit parallel shift register.
The data is shifted to 80 bit shift register at the falling
edge of the clock pulse. The clock pulse, which was
input when the enable bit (EIB/EOB) is not active
condition, is invalid.
M (38)
I Alternate signal for Alternate signal input pin for LCD driving.
LCD driver output Normal frame inversion signal is input
CL1 (49)
I Data latch clock The signal for latching the shift register contents is
input to this terminal. CL1 pulse "H" level initializes
power-down function block.
DISPOFFB I
(39)
Output level
control
(Display off)
Control input pin for display data output level (S1-
S80). V1 level is output from S1-S80 terminal during
"L" level input. LCD becomes non-selected by V1 level
output from every output of segment drivers and every
output of common drivers.
SHL (41)
I Data shift control EOB and EIB can be used as either input terminal or
output terminal according to the condition of SHL. The
shifting direction of each data, D0-D3, the I/O
condition of EOB and EIB, and the condition of SHL
are described in the table below. (refer to note 3).
Interface
Power
Supply
Power
LCD
Controller
Controller
Controller
Controller
VDD/VSS
8

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