MWCT1011AVLH 데이터 시트보기 (PDF) - NXP Semiconductors.
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MWCT1011AVLH Datasheet PDF : 857 Pages
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Section number
Title
Page
10.2.8 MCM interrupt status register (MCM_CFISR)............................................................................................. 140
10.2.9 Core fault data register (MCM_CFDTR).......................................................................................................141
10.2.10 Resource Protection Control Register (MCM_RPCR).................................................................................. 141
10.2.11 User Flash Base Address Register (MCM_UFLASHBAR).......................................................................... 143
10.2.12 User Program RAM Base Address Register (MCM_UPRAMBAR)............................................................ 143
10.2.13 Resource Protection Other Stack Pointer (MCM_SRPOSP)......................................................................... 144
10.2.14 Memory Protection Illegal PC (MCM_SRPIPC)...........................................................................................144
10.2.15 Resource Protection Misaligned PC (MCM_SRPMPC)............................................................................... 146
10.3 Functional Description..................................................................................................................................................147
10.3.1 Core Data Fault Recovery Registers.............................................................................................................. 147
Chapter 11
System Integration Module (SIM)
11.1 Introduction...................................................................................................................................................................149
11.1.1 Overview........................................................................................................................................................ 149
11.1.2 Features.......................................................................................................................................................... 149
11.1.3 Modes of Operation....................................................................................................................................... 150
11.2 Memory Map and Register Descriptions...................................................................................................................... 151
11.2.1 Control Register (SIM_CTRL)...................................................................................................................... 152
11.2.2 Reset Status Register (SIM_RSTAT)............................................................................................................ 155
11.2.3 Most Significant Half of JTAG ID (SIM_MSHID).......................................................................................156
11.2.4 Least Significant Half of JTAG ID (SIM_LSHID)....................................................................................... 157
11.2.5 Power Control Register (SIM_PWR)............................................................................................................ 157
11.2.6 Clock Output Select Register (SIM_CLKOUT)............................................................................................ 159
11.2.7 Peripheral Clock Rate Register (SIM_PCR)..................................................................................................161
11.2.8 Peripheral Clock Enable Register 0 (SIM_PCE0)......................................................................................... 162
11.2.9 Peripheral Clock Enable Register 1 (SIM_PCE1)......................................................................................... 164
11.2.10 Peripheral Clock Enable Register 2 (SIM_PCE2)......................................................................................... 165
11.2.11 Peripheral Clock Enable Register 3 (SIM_PCE3)......................................................................................... 167
11.2.12 STOP Disable Register 0 (SIM_SD0)........................................................................................................... 168
MWCT1xxx Reference Manual, Rev. 3.1, 09/2016
8
NXP Semiconductors
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