SST65P542R-8-C-SG 데이터 시트보기 (PDF) - Silicon Storage Technology

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SST65P542R-8-C-SG

Remote Controller MCU

Silicon Storage Technology 

Remote Controller MCU

SST65P542R

3.0 I/O REGISTERS AND MEMORY ORGANIZATION

Data Sheet

The SST65P542R has a total of 64 KByte of addressable memory space. A memory map is located in Figure 3-1.

The on-chip memory consists of 32 Bytes of I/O registers, 352 Bytes of SRAM, 16 KByte of user flash memory and

128 Bytes of user vectors.

FFF6H Core Timer Vector - (High Byte)

FFF7H Core Timer Vector - (Low Byte)

FFF8H

CMT Vector (High Byte)

FFF9H

CMT Vector (Low Byte)

FFFAH IRQ/Port B Vector (High Byte)

FFFBH IRQ/Port B Vector (Low Byte)

FFFCH

SWI Vector (High Byte)

FFFDH

SWI Vector (Low Byte)

FFFEH Reset Vector (High Byte)

FFFFH Reset Vector (Low Byte)

FIGURE 3-1: MEMORY MAP

Reserved

CWT Reset

0180H

3FEFH

3FF0H

3FF1H

Reserved

BFFFH

I/O

Registers

352 Bytes

SRAM

0000H

001FH

0020H

017FH

0180H

BFFFH

C000H

User

Memory

Flash Memory

(128 sectors)

16,256

Bytes

127 Sectors

(128 Bytes per sector)

Flash Memory

Read Protection FF80H

Reserved

Reset and

Interrupt

Vectors

FF81H

FFF5H

FFF6H

FFFFH

User

Vector

FF7FH

FF80H

FFFFH

1170 F02.9

©2005 Silicon Storage Technology, Inc.

7

S71170-06-000

7/05

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