CY7C1471V33
CY7C1473V33
CY7C1475V33
Truth Table
The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows.[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/Write Abort
(Begin Burst)
Write Abort
(Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Address
Used
CE1
CE2 CE3
ZZ
ADV/LD
WE
BWX OE
CEN CLK
DQ
None H X X L
L
X
X
X
L L->H Tri-State
None X X H L
L
X
X
X
L L->H Tri-State
None X L X L
L
X
X
X
L L->H Tri-State
None X X X L
H
X
X
X
L L->H Tri-State
External L H L L
L
H
X
L
L L->H Data Out (Q)
Next X X X L
H
X
X
L
L L->H Data Out (Q)
External L H L L
L
H
X
H
L L->H Tri-State
Next X X X L
H
X
X
H
L L->H Tri-State
External L H L L
L
L
L
X
L L->H Data In (D)
Next X X X L
H
X
L
X
L L->H Data In (D)
None L H L L
L
L
H
X
L L->H Tri-State
Next X X X L
H
X
H
X
L L->H Tri-State
Current X X X L
X
None X X X H
X
X
X
X
H L->H
-
X
X
X
X X Tri-State
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write
Selects are asserted, see “Truth Table for Read/Write” on page 12 for details.
3. Write is defined by BWX, and WE. See “Truth Table for Read/Write” on page 12.
4. When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document #: 38-05288 Rev. *J
Page 11 of 32