CY7C1473V33-117AXI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1473V33-117AXI
Cypress Semiconductor
CY7C1473V33-117AXI Datasheet PDF : 32 Pages
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CY7C1471V33
CY7C1473V33
CY7C1475V33
The data written during the write operation is controlled by
BWX signals. The CY7C1471V33, CY7C1473V33, and
CY7C1475V33 provides Byte Write capability that is described
in the “Truth Table for Read/Write” on page 12. The input WE
with the selected BWX input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write
operation remain unaltered. A synchronous self timed write
mechanism has been provided to simplify the write operations.
Byte write capability is included to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1471V33, CY7C1473V33, and
CY7C1475V33 are common IO devices, data must not be
driven into the device while the outputs are active. The Output
Enable (OE) can be deasserted HIGH before presenting data
to the DQs and DQPX inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs and DQPX are automati-
cally tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1471V33, CY7C1473V33, and CY7C1475V33
have an on-chip burst counter that enables the user to supply
a single address and conduct up to four write operations
without reasserting the address inputs. ADV/LD must be
driven LOW to load the initial address, as described in the
Single Write Access section. When ADV/LD is driven HIGH on
the subsequent clock rise, the Chip Enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is incre-
mented. The correct BWX inputs must be driven in each cycle
of the burst write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected before entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00
01
10
01
00
11
10
11
00
11
10
01
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min
2tCYC
0
Max
120
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Document #: 38-05288 Rev. *J
Page 10 of 32
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