EV-ADF4196SD1Z 데이터 시트보기 (PDF) - Analog Devices

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EV-ADF4196SD1Z

Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer

Analog Devices 

Data Sheet

ADF4196

PHASE REGISTER (R2) BIT LATCH MAP

12-BIT PHASE

CONTROL

BITS

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3 (0) C2 (1) C1 (0)

P12 P11

0

0

0

0

0

0

.

.

.

.

.

.

1

1

1

1

1

1

1

1

10 ≤ PHASE VALUE < MOD

P10

P3

P2

0

.......... 0

0

0

.......... 0

0

0

.......... 0

1

.

.......... .

.

.

.......... .

.

.

.......... .

.

1

.......... 1

0

1

.......... 1

0

1

.......... 1

1

1

..........

1

1

P1

PHASE VALUE1

0

0

1

1

0

2

.

.

.

.

.

.

0

4092

1

4093

0

4094

1

4095

Figure 31. Bit Map for Register R2

R2, the phase register, is used to program the phase of the VCO

output signal.

Control Bits

Register R2 is selected with C3, C2, and C1 set to 0, 1, 0.

12-Bit Phase

The 12-bit phase word sets the seed value of the Σ-Δ modulator.

It can be programmed to any integer value from 0 to MOD, where

MOD is the modulus value that is programmed in Register R1,

Bits[DB14:DB3]. As the phase word is swept from 0 to MOD,

the phase of the VCO output sweeps over a 360° range in steps

of 360°/MOD.

Note that the phase bits are double buffered; they do not take

effect until the load enable of the next write to R0 (the FRAC/INT

register). Thus, to change the phase of the VCO output frequency,

it is necessary to rewrite the INT and FRAC values to Register R0

following the write to Register R2.

The output of a fractional-N PLL can settle to any one of the

MOD possible phase offsets with respect to the reference, where

MOD is the fractional modulus.

To keep the output at the same phase offset with respect to the

reference, each time that particular output frequency is pro-

grammed, the interval between writes to Register R0 must be an

integer multiple of MOD reference cycles.

To keep the outputs of two ADF4196-based synthesizers phase

coherent with each other (but not necessarily with the reference

they have in common), the write to Register R0 on both chips

must be performed during the same reference cycle. In this

case, the interval between the R0 writes does not need to be

an integer multiple of MOD cycles.

Reserved Bit

Set the reserved bit, DB15, to 0.

Rev. D | Page 17 of 28

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