M66272FP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M66272FP Datasheet PDF : 4 Pages
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PRELIMINARY Notice:
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MITSUBISHI <DIGITAL ASSP>
M66272FP
LCD CONTROLLER with VRAM
PIN DESCRIPTIONS
Item
Pin name
Input/
Output
Function
Number
of pins
D<15:0>
Input/
Output
MPU data bus
When selecting 8 bit MPU by MPUSEL input, connect D<15:8> to VDD or VSS.
16
MPU address bus
When selecting 8-bit MPU, use A<14:0>.
A<14:0>
Input
When selecting 16-bit MPU, use A<14:1> as a address bus. By combining A<0> and BHE, access to internal
VRAM can be gained.
15
When driving two screens (dual scan mode), notice that the allowable setup range of VRAM address is
restricted. Use A<7:0> for selecting address of control register.
IOCS
Input
Chip select input of control register
When this pin is "L", select the internal control register. Assign to I/O space of MPU.
1
MCS
Input
Chip select input of VRAM
When this pin is "L", select the internal VRAM. Assign to memory space of MPU.
1
High-Write strobe input
HWR
Input When this pin is "L", write data to the internal VRAM. HWR is valid only in using 16-bit MPU
1
controlled byte access by LWR and HWR.
LWR
Input
Low-Write strobe input
When this pin is "L", write data to the internal control register or VRAM.
1
RD
MPU
Read strobe input
Input When this pin is "L", read data from the internal control register or VRAM.
1
interface MPUSEL Input
8/16-bit MPU select input
According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU.
1
Reset input
RESET Input Use reset signal of MPU. When this pin is "L", initialize (reset) all internal control registers and
1
counters.
MPUCLK Input
MPU clock
Input system clock output from MPU.
1
Bus-High-Enable input
BHE
Input This pin is valid when using 16-bit MPU controlling byte access with A<0> and BHE.
1
Connect to "VDD" to select 8-bit MPU.
Bus swap input
When selecting 16-bit MPU, connect SWAP to “VSS” to transfer VD<n:0> in order of Upper/Lower byte of
SWAP
Input MPU data bus, reversally connect to “VDD” in order of Lower/Upper byte.
1
When selecting 8-bit MPU, connect to “VSS”. Even if connecting to “VDD”, use D<7:0> to access to register of
8-bit width.
WAIT
WAIT output for MPU
This signal makes WAIT for MPU. Change WAIT to "L" at timing of falling edge of overlapping with MCS and
Output RD or LWR and HWR. And return to "H" at synchronization with the rising edge of MPUCLK after internal 1
processing. (Output WAIT only when requested access from MPU to VRAM is gained during cycle steal
access.)
CSE
Cycle Steal Enable output
Output State output of internal cycle steal access.
1
Display data bus for LCD
VD<7:0> Output Transfer the LCD display data in synchronization with a rising edge of CP by putting 4-bit or 8-bit in parallel.
8
The VD<n:0> output pin in use differs depending on the number of driven screens and the display mode.
Display data transfer clock
CP
Output Shift clock for the transfer of display data to LCD.
1
Take the display data of VD<n:0> to LCD at falling edge of CP.
Display data latch pulse
This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal.
LP
Output LP is output when it finishes transferring display data of a line.
1
LCD
Latch of display data and the transfer of scanning signal at falling edge of LP.
interface
First Line Marker signal output
FLM
Output Output the start pulse of scanning line.
1
This signal is "H" active, the IC for driving scanning line catches FLM at falling edge of LP.
M
Output LCD alternating signal output
Signal for driving LCD by alternating current.
1
LCD (ON/OFF) control signal output
LCDENB Output Output data which is set at bit "0" of mode register (R1) in the control register. This signal can be 1
used for controlling the LCD power supply, because LCDENB is set to "L" by RESET.
VDD
Power supply pin
7
Others VSS
Ground
12
N.C
No connection
5
3
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