AD5554BRS 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
AD5554BRS Datasheet PDF : 16 Pages
| |||
AD5544/AD5554
AD5544/AD5554 PIN FUNCTION DESCRIPTIONS
Pin # Name
1
AGNDA
2
IOUTA
3
VREFA
4
RFBA
5 MSB
6
RS
7
VDD
8
CS
9 CLK
10 SDI
11 RFBB
12 VREFB
13
IOUTB
14 AGNDB
15 AGNDC
16
IOUTC
17 VREFC
18 RFBC
19 NC
20 SDO
21 LDAC
22 AGNDF
23 VSS
24 DGND
25 RFBD
26 VREFD
27
IOUTD
28 AGNDD
Function
DAC A Analog Ground.
DAC A Current Output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.
Establish Voltage Output for DAC A by Connecting to External Amplifier Output.
MSB Bit Set Pin During a Reset Pulse (RS) or at System Power ON if Tied to Ground or VDD.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for
AD5544 and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB
= 0. Register Data = 8000H for AD5544 and 2000H for AD5554 when MSB = 1.
Positive Power Supply Input. Specified range of operation 5 V ± 10%.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the Input
Register when CS/LDAC returns High. Does not effect LDAC operation.
Clock Input, Positive Edge Clocks Data into Shift Register.
Serial Data Input, Input Data Loads Directly into the Shift Register.
Establish Voltage Output for DAC B by Connecting to External Amplifier Output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.
DAC B Current Output.
DAC B Analog Ground.
DAC C Analog Ground.
DAC C Current Output.
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.
Establish voltage output for DAC C by connecting to external amplifier output.
No Connect. Leave pin unconnected.
Serial Data Output, input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for
AD5544 and 17 clock pulses for AD5554 after input at the SDI pin.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to DAC registers. Asyn-
chronous active low input. See Control Logic Truth Table for operation.
High Current Analog Force Ground.
Negative Bias Power Supply Input. Specified range of operation –0.3 V to –5.5 V.
Digital Ground Pin.
Establish Voltage Output for DAC D by Connecting to External Amplifier Output.
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.
DAC D Current Output.
DAC D Analog Ground.
AD5544/AD5554 PIN CONFIGURATION
AGNDA 1
28 AGNDD
IOUTA 2
27 IOUTD
VREFA 3
26 VREFD
RFBA 4
25 RFBD
MSB 5
RS 6
AD5544/
AD5554
24 DGND
23 VSS
VDD 7 TOP VIEW 22 AGNDF
CS 8 (Not to Scale) 21 LDAC
CLK 9
20 SDO
SDI 10
19 NC
RFBB 11
VREFB 12
IOUTB 13
AGNDB 14
18 RFBC
17 VREFC
16 IOUTC
15 AGNDC
NC = NO CONNECT
–8–
REV. 0
Share Link: 