ISL97651 데이터 시트보기 (PDF) - Renesas Electronics
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ISL97651 Datasheet PDF : 20 Pages
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ISL97651
Pin Descriptions
PIN NUMBER
PIN NAME
1
VIN1
2
LX1
3
LX2
4
CB
5
LXL
6
VSUP
7
FBL
8
CM2
9
CTL
10, 18, 28, 36
NC
11
DRN
12
COM
13
14
15
16
17
19
20
21
22
23
24
25, 26
27
29
30
31
32
33
34
35
(Exposed Die Plate)
POUT
C1-
C1+
C2-
C2+
FBP
VREF
FBN
PGND3
NOUT
VINL
PGND2, 1
AGND
CDEL
ENL
DELB
CM1
VIN2
FBB
EN
N/A
DESCRIPTION
Input voltage, connect to pin 33 (VIN2)
Internal boost switch connection
Internal boost switch connection
Logic buck, boost strap pin
Buck converter output
Positive supply for charge pumps
Logic buck feedback pin
Buck compensation network pin
Input control for VON slice output
No connect. Connect to die pad and GND for improved thermal efficiency.
Lower reference voltage for VON slice output
VON slice output: when CTL = 1, COM is connected to SRC through a 5 resistor; when CTL = 0, COM
is connected to DRN through a 30 resistor.
Positive charge pump out
Charge pump capacitor 1, negative connection
Charge pump capacitor 1, positive connection
Charge pump capacitor 2, negative connection
Charge pump capacitor 2, positive connection
Positive charge pump feedback pin
Reference voltage
Negative charge pump feedback pin
Power ground for VOFF, VON and VON slice
Negative charge pump output
Logic buck supply voltage
Boost power grounds
Signal ground pin
Delay capacitor for start up sequencing, soft-start and fault detection timers.
Buck enable for VLOGIC output
Open drain NFET output to drive optional AVDD delay PFET
Boost compensation network pin
Input voltage, connect to pin 1 (VIN1)
Boost feedback pin
Enable for Boost, charge pumps and VON slice (independent of ENL).
Connect exposed die plate on rear of package to ACGND and the PGND1, 2 pins. See “Layout
Recommendation” on page 18 for PCB layout thermal considerations.
FN7493 Rev 3.00
April 24, 2009
Page 8 of 20
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