ISL8022 데이터 시트보기 (PDF) - Renesas Electronics

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ISL8022

Dual 2A/1.7A Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator

Renesas Electronics 

ISL8022

Ordering Information

PART NUMBER PART TEMP.RANGE PACKAGE PKG.

(Notes 1, 2, 3) MARKING (°C)

(Pb-Free) DWG. #

ISL8022IRZ

8022

-40 to +85 12 Ld 4x3 DFN L12.4x3

ISL8022EVAL1Z Evaluation Board

ISL8022EVAL2Z Evaluation Board

NOTES:

1. Add “T” suffix for Tape and Reel. Please refer to TB347 for details

on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-

free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is

RoHS compliant and compatible with both SnPb and Pb-free

soldering operations). Intersil Pb-free products are MSL classified

at Pb-free peak reflow temperatures that meet or exceed the Pb-

free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information

page for ISL8022. For more information on MSL please see

techbrief TB363.

Pin Configuration

ISL8022

(12 LD DFN)

TOP VIEW

FB1 1

EN1 2

PG 3

VIN1 4

LX1 5

PGND1 6

PAD

12 FB2

11 EN2

10 SYNC

9 VIN2

8 LX2

7 PGND2

Pin Description

PIN

NUMBER

1

2

3

4

5

6

7

8

9

10

11

12

-

SYMBOL

FB1

EN1

PG

VIN1

LX1

PGND1

PGND2

LX2

VIN2

SYNC

EN2

FB2

EXPOSED

PAD

DESCRIPTION

The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The

output voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage

can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal

compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry

use FB1 to monitor the Channel 1 regulator output voltage.

Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and discharge output

capacitor when driven to low. Do not leave this pin floating.

1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed Power-Good signal for both the VOUT1 and VOUT2

voltages. There is an internal 1M pull-up resistor.

Input supply voltage for Channel 1. Connect 10µF ceramic capacitor to PGND1.

Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1.

Negative supply for power stage 1.

Negative supply for power stage 2 and system ground.

Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.

Input supply voltage for Ch 2 and to provide logic bias. Make sure that VIN2 is ≥ VIN1. Connect 10µF ceramic capacitor to

PGND2.

Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low or ground for forced PWM

mode. Connect to an external function generator for Synchronization. Negative edge trigger. Do not leave this pin floating.

Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2 and discharge output

capacitor when driven to low. Do not leave this pin floating.

The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The

output voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage

can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal

compensation to meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry

use FB2 to monitor the Channel 2 regulator output voltage.

The exposed pad must be connected to the SGND pin for proper electrical performance. Add as much vias as possible for

optimal thermal performance.

FN7650 Rev 3.00

March 14, 2013

Page 4 of 18

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