ISL6263 데이터 시트보기 (PDF) - Renesas Electronics
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ISL6263 Datasheet PDF : 19 Pages
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ISL6263
TABLE 2. VID TABLE FOR INTEL IMVP-6+ VCCGFX
CORE (Continued)
VCCGFX
VID4 VID3 VID2 VID1 VID0
(V)
1
0
0
1
0 0.82400V
1
0
0
1
1 0.79825V
1
0
1
0
0 0.77250V
1
0
1
0
1 0.74675V
1
0
1
1
0 0.72100V
1
0
1
1
1 0.69525V
1
1
0
0
0 0.66950V
1
1
0
0
1 0.64375V
1
1
0
1
0 0.61800V
1
1
0
1
1 0.59225V
1
1
1
0
0 0.56650V
1
1
1
0
1 0.54075V
1
1
1
1
0 0.51500V
1
1
1
1
1 0.41200V
Theory of Operation
The R3 Modulator
The heart of the ISL6263 is Intersil’s Robust-Ripple-Regulator
(R3) Technology™. The R3 modulator is a hybrid of fixed
frequency PWM control, and variable frequency hysteretic
control that will simultaneously affect the PWM switching
frequency and PWM duty cycle in response to input voltage
and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal VR that appears
across the internal ripple-capacitor CR. The VR signal is a
representation of the output inductor ripple current.
Transconductance amplifiers measuring the input voltage of
the converter and the output set-point voltage VSOFT, together
produce the voltage-ripple signal VR.
A voltage window signal VW is created across the VW and
COMP pins by sourcing a current proportional to gmVsoft
through a parallel network consisting of resistor RFSET and
capacitor CFSET. The synthesized voltage-ripple signal VR
along with similar companion signals are converted into PWM
pulses.
The PWM frequency is proportional to the difference in
amplitude between VW and VCOMP. Operating on these large-
amplitude, low noise synthesized signals allows the ISL6263 to
achieve lower output ripple and lower phase jitter than either
conventional hysteretic or fixed frequency PWM controllers.
Unlike conventional hysteretic converters, the ISL6263 has an
error amplifier that allows the controller to maintain tight
voltage regulation accuracy throughout the VID range from
0.41200V to 1.28750V.
Power-On Reset
The ISL6263 is disabled until the voltage at the VDD pin has
increased above the rising VDD power-on reset (POR)
VDD_THR threshold voltage. The controller will become
disabled when the voltage at the VDD pin decreases below the
falling POR VDD_THF threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263 start-up timing. Once VDD has
ramped above VDD_THR, the controller can be enabled by
pulling the VR_ON pin voltage above the input-high threshold
VVR_ONH. Approximately 100µs later, the soft-start capacitor
CSOFT begins slewing to the designated VID set-point as it is
charged by the soft-start current source ISS. The VCCGFX
output voltage of the converter follows the VSOFT voltage ramp
to within 10% of the VID set-point then counts 6 switching
cycles, then changes the open-drain output of the PGOOD pin
to high impedance. During soft-start, the regulator always
operates in continuous conduction mode (CCM).
VR_ON
~100µs
VSOFT/ VCCGFX
90%
PGOOD
6 SWITCHING CYCLES
FIGURE 4. ISL6263 START-UP TIMING
Static Regulation
The VCCGFX output voltage will be regulated to the value set
by the VID inputs per Table 2. A true differential amplifier
connected to the VSEN and RTN pins implements processor
socket Kelvin sensing for precise core voltage regulation at the
GPU voltage sense points.
As the load current increases from zero, the VCCGFX output
voltage will droop from the VID set-point by an amount
proportional to the IMVP-6+ load line. The ISL6263 can
accommodate DCR current sensing or discrete resistor current
sensing. The DCR current sensing uses the intrinsic series
resistance of the output inductor as shown in the application
circuit of Figure 2. The discrete resistor current sensing uses a
shunt connected in series with the output inductor as shown in
the application circuit of Figure 3. In both cases the signal is
fed to the non-inverting input of the DROOP amplifier at the
VSUM pin, where it is measured differentially with respect to
the output voltage of the converter at the VO pin and amplified.
The voltage at the DROOP pin minus the output voltage
measured at the VO pin, is proportional to the total inductor
FN9213 Rev 2.00
June 10, 2010
Page 10 of 19
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