ISL6223 데이터 시트보기 (PDF) - Renesas Electronics

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ISL6223

Mobile Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller

Renesas Electronics 

ISL6223

the 5V supply rises. The PGOOD output stage is made up of

NMOS and PMOS transistors. On the rising VCC, the PMOS

device becomes active slightly before the NMOS transistor

pulls “down”, generating the slight rise in the PGOOD

voltage.

Note that Figure 5 shows the 12V battery voltage available

before the 5V supply to the ISL6223 has reached its

threshold level. If conditions were reversed and the 5V

supply was to rise first, the start-up sequence would be

different. In this case, the ISL6223 will sense an overcurrent

condition due to charging the output capacitors. The supply

will then restart and go through the normal Soft-Start cycle.

DELAY TIME

PWM 1

OUTPUT

PGOOD

VCORE

EN

SWITCH

VIN = 12V

FIGURE 3. START-UP OF A SYSTEM OPERATING AT 200kHz

DELAY TIME

V COMP

PGOOD

VCORE

EN

SWITCH

VIN = 12V

FIGURE 4. START-UP A SYSTEM OPERATING AT 200kHz

.

12V

SUPPLY

DELAY TIME

PGOOD

VCORE

5V

SUPPLY

FIGURE 5. SUPPLY POWERED BY ATX SUPPLY

Fault Protection

The ISL6223 protects the microprocessor and the entire

power system from damaging stress levels. Within the

ISL6223 both Overvoltage and Overcurrent circuits are

incorporated to protect the load and regulator.

Overvoltage

The VSEN pin is connected to the microprocessor CORE

voltage. A CORE overvoltage condition is detected when the

VSEN pin goes above 2.35V.

The overvoltage condition is latched, disabling normal PWM

operation, and causing PGOOD to go low. The latch can

only be reset by lowering and returning VCC high to initiate a

POR and Soft-Start sequence.

During a latched overvoltage, the PWM outputs will be

driven either low or three state, depending upon the VSEN

input. PWM outputs are driven low when the VSEN pin

detects that the CORE voltage is above 2.35V. This

condition drives the PWM outputs low, resulting in the lower

or synchronous rectifier MOSFETs to conduct and shunt the

CORE voltage to ground to protect the load.

If after this event, the CORE voltage falls below 1.7V, the

PWM outputs will be three state. The HIP6601 family of

drivers pass the three state information along, and shut off

both upper and lower MOSFETs. This prevents “dumping” of

the output capacitors back through the lower MOSFETs,

avoiding a possibly destructive ringing of the capacitors and

output inductors. If the conditions that caused the

overvoltage still persist, the PWM outputs will be cycled

between three state and VCORE clamped to ground, as a

hysteretic shunt regulator.

Undervoltage

The VSEN pin also detects when the CORE voltage falls

below 0.9V level. This causes PGOOD to go low, but has no

other effect on operation and is not latched. There is also

hysteresis in this detection point.

FN9013 Rev 3.00

July 9, 2008

Page 8 of 15

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