12032IVZ 데이터 시트보기 (PDF) - Renesas Electronics

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12032IVZ

Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Crystal Back-up

Renesas Electronics 

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

1. Real Time Clock (8 bytes): Address 00h to 07h.

2. Status (2 bytes): Address 08h to 09h.

3. Counter (2 bytes): Address Ah to Bh.

4. Control (9 bytes): 0Ch to 14h.

5. Day Light Saving Time (8 bytes): 15h to 1Ch

6. Alarm 0/1 (12 bytes): 1Dh to 28h

7. Time Stamp for Battery Status (5 bytes): Address 29h to

2Dh.

8. Time Stamp for VDD Status (5 bytes): Address 2Eh to 32h.

9. Time Stamp for Event Status (5 bytes): 33h to 37h.

Write capability is allowable into the RTC registers (00h to 07h)

only when the WRTC bit (bit 6 of address 0Ch) is set to “1”.

Other sections do not need to have the WRTC bit set for write

access. A read or write can begin at any address within the

section. A write to sections 2 through 9 can be continuous. A

write can overlap two or more sections as well.

A register can be read by performing a random read at any

address at any time. This returns the contents of that register

location. Additional registers are read by performing a

sequential read. For the RTC and Alarm registers, the read

instruction latches all clock registers into a buffer, so an update

of the clock does not change the time being read. At the end of

a read, the master supplies a stop condition to end the

operation and free the bus. After a read, the address remains

at the previous address +1 so the user can execute a current

address read and continue reading the next register.

It is only necessary to set the WRTC bit prior to writing into the

RTC registers. All other registers are completely accessible

without setting the WRTC bit.

FN6618 Rev 3.00

May 5, 2011

Page 11 of 26

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