ICSSSTV16859C 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICSSSTV16859C Datasheet PDF : 8 Pages
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ICSSSTV16859C
General Description
The 13-bit-to-26-bit ICSSSTV16859C is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2
I/O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16859C supports low-
power standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset
to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that
RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during
power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic “Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable
the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
Pin Configuration (64-Pin TSSOP)
PIN NUMBER
1-5, 8-14, 16, 17, 19-25, 28-32
7, 15, 26, 34, 39, 43, 50, 54,
58, 63
6, 18, 27, 33, 38, 47, 59, 64
35, 36, 40-42, 44, 52, 53, 55-
57, 61, 62
48
49
37, 46, 60
51
45
PIN NAME
Q (13:1)
GND
VDDQ
D (13:1)
CLK
CLK#
VDD
RESET#
VREF
TYPE
OUTPUT
PWR
PWR
INPUT
INPUT
INPUT
PWR
INPUT
INPUT
Data output
DESCRIPTION
Ground
Output supply voltage, 2.5V nominal
Data input
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
Input reference voltage, 2.5V nominal
Pin Configuration (56-Pin MLF2)
PIN NUMBER
1-8, 10-16, 18-22, 50-54, 56
37, 48
9, 17, 23, 27, 34, 44, 49, 55
24, 25, 28-31, 39-43, 46, 47
35
36
26, 33, 45
38
32
-
PIN NAME
Q (13:1)
GND
VDDQ
D (13:1)
CLK
CLK#
VDD
RESET#
VREF
Center PAD
TYPE
OUTPUT
PWR
PWR
INPUT
INPUT
INPUT
PWR
INPUT
INPUT
PWR
DESCRIPTION
Data output
Ground
Output supply voltage, 2.5V nominal
Data input
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
Input reference voltage, 2.5V nominal
Ground (MLF2 package only)
0703A—10/15/02
2
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