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MX29LV161DB 데이터 시트보기 (PDF) - Macronix International

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MX29LV161DB
MCNIX
Macronix International MCNIX
MX29LV161DB Datasheet PDF : 63 Pages
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MX29LV161D T/B
GENERAL DESCRIPTION
MX29LV161DT/B is a 16Mbit flash memory that can be organized as 1,048,576 words. These devices operate
over a voltage range of 2.7V to 3.6V typically using a 3V power supply input. The memory array is divided into 32
equal 64 Kilo byte blocks. However, depending on the device being used as a Top-Boot or Bottom-Boot device.
The outermost two sectors at the top or at the bottom are respectively the boot blocks for this device.
The MX29LV161DT/B is offered in a 48-pin TSOP, 48-ball XFLGA/WFBGA and a 48-ball CSP(TFBGA) JEDEC
standard package. These packages are offered lead-free versions that are compliant to the RoHS specifications.
The software algorithm used for this device also adheres to the JEDEC standard for single power supply devic-
es. These flash parts can be programmed in system or on commercially available EPROM/Flash programmers.
Separate OE# and CE# (Output Enable and Chip Enable) signals are provided to simplify system design. When
used with high speed processors, the 90ns read access time of this flash memory permits operation with minimal
time lost due to system timing delays.
The automatic write algorithm provided on Macronix flash memories perform an automatic erase prior to write.
The user only needs to provide a write command to the command register. The on-chip state machine automati-
cally controls the program and erase functions including all necessary internal timings. Since erase and write
operations take much longer time than read operations, erase/write can be interrupted to perform read opera-
tions in other sectors of the device. For this, Erase Suspend operation along with Erase Resume operation are
provided. Data# polling or Toggle bits are used to indicate the end of the erase/write operation.
These devices are manufactured at the Macronix fabrication facility using the time tested and proven MXIC's
advance technology. This proprietary non-epi process provides a very high degree of latch-up protection for
stresses up to 100 milliamperes on address and data pins from -1V to 1.5xVCC.
With low power consumption and enhanced hardware and software features, this flash memory retains data reli-
ably for at least twenty years. Erase and programming functions have been tested to meet a typical specification
of 100,000 cycles of operation.
P/N:PM1359
REV. 1.0, JUN. 03, 2010
6

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