ML7012-06 데이터 시트보기 (PDF) - LAPIS Semiconductor Co., Ltd.
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ML7012-06 Datasheet PDF : 23 Pages
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BLOCK DIAGRAM
RTS
CTS
DCD
DSR
DTR
CI
STD
SRD
UART
SPEED1, 0
PDN/RST
OSC0
OSC1
TST2 to 0
TI8 to 0
TO10 to 0
VDD2, 1
GND2, 1
Clock
generation
To each
section
FEDL7012-06-02
ML7012-06
ML7012-06
RLY2
RLY1
Modulation/
demodulation
–
+
–
+
Tone
generation
AFE
AOUT
RCI
RCAO
TXAI
TXAN
Tone
detection
–
+
TXAP
–
AIN
+
GSR
SG Gen.
SG
SPK
RII
VDDA
GNDA
2/23
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