SwitchRegTM
PRODUCT DATASHEET
AAT1142
800mA Voltage-Scaling Step-Down Converter
Characteristics of SDA and SCL Bus Lines
Parameter
SCL Clock Frequency Hold Time for START Condition; After this
Period, the First Clock Pulse is Generated
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data in Hold Time
Data in Set-Up Time
Set-Up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Input Low Level
Input High Level
Symbol
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
VIL
VIH
Standard Mode
Min
4.0
4.7
4.0
4.7
0
350
4.0
4.7
VIN · 0.7
Max
100
3.45
VIN · 0.3
Fast Mode
Min
0.6
1.3
0.6
0.6
0
350
0.6
1.3
VIN · 0.7
Max
400
0.9
VIN · 0.3
Units
kHz
μs
μs
μs
μs
μs
ns
μs
μs
V
V
1142.2009.08.1.1
www.analogictech.com
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