SL4516BN 데이터 시트보기 (PDF) - System Logic Semiconductor
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SL4516BN Datasheet PDF : 6 Pages
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SL4516B
AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kΩ, Input tr=tf=20 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V ≥-55°C 25°C ≤125°C Unit
tPHL, tPLH Maximum Propagation Delay, Clock to Q (Figure 5.0
400
400
800
ns
1)
10
200
200
400
15
150
150
300
tPHL, tPLH Maximum Propagation Delay, Preset or Reset to 5.0
420
420
840
ns
Q (Figure 1)
10
210
210
420
15
160
160
320
tPHL, tPLH Maximum Propagation Delay, Clock to Carry Out 5.0
480
480
960
ns
(Figure 1)
10
240
240
480
15
180
180
360
tPHL, tPLH Maximum Propagation Delay, Carry In to Carry
5.0
250
250
500
ns
Out (Figure 1)
10
120
120
240
15
100
100
200
tPHL, tPLH Maximum Propagation Delay, Preset or Reset to 5.0
640
640
1280
ns
Carry Out (Figure 1)
10
320
320
640
15
250
250
500
tTHL, tTLH Maximum Output Transition Time, Any Output 5.0
200
200
400
ns
(Figure 1)
10
100
100
200
15
80
80
160
CIN
Maximum Input Capacitance
-
7.5
pF
TIMING REQUIREMENTS(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V ≥-55°C 25°C ≤125°C Unit
tsu
Minimum Setup Time, P to Preset Enable
(Figure 1)
5.0
25
25
50
ns
10
10
10
20
15
10
10
20
tsu
Minimum Setup Time, Up/Down to Clock
5.0
ns
(Figure 1)
10
15
tsu
Minimum Setup Time, Carry In to Clock
5.0
ns
(Figure 1)
10
15
th
Minimum Hold Time, Clock to Carry In (Figure 1) 5.0
60
60
120
ns
10
30
30
60
15
30
30
60
th
Minimum Hold Time, Clock to Up/Down (Figure 5.0
30
30
60
ns
1)
10
30
30
60
15
30
30
60
th
Minimum Hold Time, Preset enable to P (Figure 5.0
70
70
140
ns
1)
10
40
40
80
15
40
40
80
SLS
System Logic
Semiconductor
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