HI5660 데이터 시트보기 (PDF) - Intersil
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HI5660 Datasheet PDF : 9 Pages
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HI5660
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . -0.3V To +0.3V Digital Input Voltages
(D9-D0, CLK, SLEEP) . . . . . . . . . . . . . . . . . . . . . . . . . DVDD + 0.3V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . ±50µA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
117
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values
TA = -40oC TO 85oC
TEST CONDITIONS
MIN TYP MAX
UNITS
SYSTEM PERFORMANCE
Resolution
8
-
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
-0.5 ±0.25 +0.5
LSB
Differential Linearity Error, DNL
(Note 7)
-0.5 ±0.25 +0.5
LSB
Offset Error, IOS
Offset Drift Coefficient
(Note 7)
(Note 7)
-0.025
+0.025 % FSR
-
0.1
-
ppm
FSR/oC
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
-10
±2
+10 % FSR
With Internal Reference (Notes 2, 7)
-10
±1
+10 % FSR
Full Scale Gain Drift
With External Reference (Note 7)
-
±50
-
ppm
FSR/oC
With Internal Reference (Note 7)
-
±100
-
ppm
FSR/oC
Full Scale Output Current, IFS
Output Voltage Compliance Range
(Note 3)
2
-
20
mA
-0.3
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
Output Settling Time, (tSETT)
(Notes 3, 9)
0.8% (±1 LSB, equivalent to 7 Bits) (Note 7)
0.4% (±1/2 LSB, equivalent to 8 Bits) (Note 7)
125
-
-
MHz
-
5
-
ns
-
15
-
ns
Singlet Glitch Area (Peak Glitch)
Output Rise Time
RL = 25Ω (Note 7)
Full Scale Step
-
5
-
pV•s
-
1.5
-
ns
Output Fall Time
Full Scale Step
-
1.5
-
ns
Output Capacitance
10
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/ √Hz
IOUTFS = 2mA
-
30
-
pA/ √Hz
3
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