SC3040B 데이터 시트보기 (PDF) - Murata Manufacturing
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SC3040B Datasheet PDF : 2 Pages
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• Quartz SAW Frequency Stability
• Fundamental Fixed Frequency
• Excellent Jitter and Symmetry
• Rugged, Miniature, Surface-Mount Case
• Low-Voltage Power Supply (3.3 VDC)
• Directive 2002/95/EC (ROHS) Compliant by June, 2006
This digital clock is designed for use in telecom applications; such as Timing for Terabit Router applications.
Fundamental-mode oscillation is made possible by surface-acoustic-wave (SAW) technology. The design
results in low jitter, compact size, and low power consumption. Differential outputs provide a sine wave that is
made to drive 50 Ω loads.
Absolute Maximum Ratings
Rating
Value
Units
Power Supply Voltage (VCC at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
0 to +4.0
0 to +4.0
VDC
VDC
Case Temperature (Powered or Storage)
-40 to +85
°C
RFM products are now
Murata products.
SC3040B
400.0 MHz
Differential
Sine-Wave Clock
SMC-8 Case
Electrical Characteristics
Characteristic
Output Frequency
Q and Q Output
Absolute Frequency
Tolerance from 400.000 MHz
Power 50Ω (VSWR ≤ 1.2)
Operating Load VSWR
Sym
fO
ΔfO
PO
Notes
1, 2
1, 3
Minimum
399.920
0.5
Typical
Maximum
400.080
±200
5.5
2:1
Units
MHz
ppm
dBm
Symmetry
3, 4, 5
49
51
%
Harmonic Spurious
Nonharmonic Spurious
3, 4, 6
-25
-20
dBc
-60
dBc
Q and Q Period Jitter
Output (Disabled)
No Noise on VCC
200 mVP-P from 1 MHz to ½ fO on
Amplitude into 50 Ω
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
DC Power Supply
Operating Voltage
Operating Current
Operating Ambient Temperature
Lid Symbolization (YY = Year, WW = Week)
3, 4, 6, 7
15
30
3, 4, 7, 8
35
3, 9
75
3
100
VIH
VCC-0.1
VCC
VCC+0.1
VIL
0.0
0.20
IIH
3, 9
3
5
IIL
-1
tPD
1
VCC
ICC
1, 3
+3.13
+3.30
18
+3.47
40
TA
1, 3
0
+70
RFM SC3040B 400.00 MHz YYWW
psP-P
psP-P
mVP-P
KΩ
V
V
mA
mA
ms
VDC
mA
°C
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1. Unless otherwise noted, all specifications include any combination of load
6. Jitter and other spurious outputs induced by externally generated electrical noise
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 Ω loads to
ground. (See: Typical Test Circuit.)
on VCC or mechanical vibration are not included. Dedicated external voltage
regulation and careful PCB layout are recommended for optimum performance.
2. One or more of the following United States patents apply: 4,616,197; 4,670,681; 7. Applies to period jitter of Q and Q. Measurements are made with the Tektronix
4,760,352.
CSA803 signal analyzer with at least 1000 samples.
3.
4.
5.
The design, manufacturing process, and specifications of this device are subject 8.
to change without notice.
Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and
nominal power supply voltage.
9.
Symmetry is defined as the pulse width (in percent of total period) measured at
the 50% points of Q or Q. (See: Timing Definitions.)
Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half
of fO at the VCC power supply terminal.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is
defined as the time from the 50% point on the rising edge of ENABLE to the 90%
point on the rising edge of the output amplitude or as the fall time from the 50%
point to the 10% point. (SEE: Timing Definitions.)
©2010-2015 by Murata Electronics N.A., Inc.
SC3040B (R) 2/17/15
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www.murata.com
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