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SC2677B

Dual Synchronous Voltage Mode Controller with Current Sharing Circuitry

Semtech Corporation 

POWER MANAGEMENT

Pin Configuration

Top View

SC2677B

Ordering Information

Devi ce(1)

SC2677BITSTRT(2)

SC2677BTETRT(2)

SC2677BEVB-1

SC2677BEVB-2

Package

TSSOP-24

TSSOP-24 EDP

Current Share Evaluation Board

Dual Channel Evaluation Board

Notes:

(1) Only available in tape and reel packaging. A reel con-

tains 2500 devices.

(2) Lead free package. Device is fully WEEE and RoHS

compliant.

(TSSOP-24 Pin)

Pin Descriptions

EXPANDED PIN DESCRIPTION

Pin 1, 24: (CS2+, CS1+)

Current sense amplifier (for OCP protection) non-inverting

inputs.

Pin 2, 23: (CS2-, CS1-)

Current sense amplifier (for OCP protection) inverting

inputs.

Pin 3: (VREF)

Internal 0.5V reference. Connected to the + input of the

master channel error amplifier.

Pin 4: (FREQ)

External frequency adjustment. Connect a resistor to

AGND to set the switching frequency. Please see more

information in Application section.

Pin 5: (VCC)

Bias pin for the controller. Connect a ceramic decoupling

capacitor from this pin to AGND with minimum trace

length.

Pin 6: (+IN2)

“+” input of the slave error amplifier.

Pin 7, 18: (-IN2, -IN1)

“-” inputs of the error amplifiers.

Pin 8, 17: (COMP2, COMP1)

Compensation pins of the error amplifiers.

Pin 9, 16: (BST2, BST1)

Supply pins for the high side drivers. Usually connected

to bootstrap circuit.

Pin 10, 15: (DH2, DH1)

Gate drive pins for the top MOSFETs. Requires a small

series resistor.

Pin 11, 14: (DL2, DL1)

Gate drive pins for the bottom MOSFETs. Requires a

small series resistor.

Pin 12: (PGND)

Power GND. Return of the high side and low side gate

drivers.

Pin 13: (BSTC)

Supply pin for bottom MOSFET gate drivers.

Pin 19: (PHASING)

This pin controls the phase shift between master and

slave for optimum noise immunity. Use a resistive

divider from the FREQ pin (pin 2) to AGND, and connect

the tap of the resistive divider to pin 17. Please see

more information in Application section.

Pin 20: (SS/ENA)

Soft start pin. Connect a ceramic capacitor from this pin

to AGND, and there is an internal current source charg-

ing up this capacitor during soft start. The PWM opera-

tion can be disabled if this pin is pulled low.

Pin 21: (PWRGD)

Power good signal. This is an open collector output. It is

pulled low internally if output voltage is outside the

power good window.

Pin 22: (GND)

Analog GND. Return of the analog signals and bias of

the chip.

© 2009 Semtech Corp.

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