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SC2677B(2004) 데이터 시트보기 (PDF) - Semtech Corporation

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SC2677B Datasheet PDF : 19 Pages
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SC2677B
POWER MANAGEMENT
Application Information
Main Loop(s)
The SC2677B is a dual-voltage mode synchronous Buck
controller. The two separate channels are identical and
share only IC supply pins (Vcc and GND), output driver
ground (PGND) and pre-driver supply voltage (BSTC). They
also share a common oscillator generating a sawtooth
waveform for Channel 1 and an dephased sawtooth for
Channel 2. Both Error Amplifier inputs on Channel 2 in-
puts are uncommitted and available externally. This al-
lows the SC2677B to operate in two distinct modes.
a) Two independent channels with either common or
different input voltages and different output voltages.
The two channels each have their own voltage feed-
back path from their own output. In this mode, posi-
tive input of the Error Amplifier 2 is connected exter-
nally to Vref. If the application uses a common input
voltage, the sawtooth phase shift between the chan-
nels provides some measure of input ripple current
cancellation.
b) Two channels operating in current sharing mode
with common output voltage and either common in-
put voltage or different input voltages. In this mode,
Channel 1 operates as a voltage mode Buck controller,
as before, but Error Amplifier 2 monitors and ampli-
fies the difference in voltage across the output cur-
rent sense resistors of Channel 1 and Channel 2 (Mas-
ter and Slave) and adjusts the Slave duty cycle to
match output currents. To controller also works well
for using the output choke winding resistance as cur-
rent sensing element (please refer the “Application”
schematic for details). The amount of the current of
the Slave Channel vs. the Master Channel can be pro-
grammed according to the application. This feature is
especially useful when two input sources are used and
each source has its own power budget.
Soft Start/Enable
The Soft Start/Enable (SS/ENA) pin serves several func-
tions. If held below the Enable threshold, both channels
are inhibited. DH1 and DH2 will be low, turning off the
top FETs. Between the Soft Start Enable threshold and
the Soft Start End threshold, the duty cycle is allowed to
increase. At the Soft Start End threshold, maximum duty
cycle is reached. In practical applications, the Error Am-
plifier will control the duty cycle before the Soft Start
End threshold is reached. To avoid boost problems dur-
ing startup in current share mode, both channels start
up in asynchronous mode, and the bottom FET body di-
ode is circulates current during the top FET off time. When
the SS/ENA pin reaches the Soft Start Transition thresh-
old, the channels begin operating in synchronous mode
for improved efficiency. The Soft Start pin sources ap-
proximately 50uA, and Soft Start timing can be set by
selection of an appropriate Soft Start capacitor value.
Frequency Set and Phasing
The switching frequency can be programmed by connect-
ing a resistor from the FREQ pin to AGND. The PHASING
pin controls the phase shift between the Master sawtooth
and Slave sawtooth which allows the adjustment of the
phase shift for maximum noise immunity by controlling
the timing between Master and Slave transition. A resis-
tive divider is used from the FREQ pin to AGND and the
divided voltage is fed to the PHASING pin as depicted.
R13
R19
SC2677B
The offset of the current sharing Error Amplifier is
trimmed within the range of -2mV to 0mV. The Slave
is OFF if the Master has no current.
Power Good
The controller provides a Power Good signal. This is an
open-collector output, which is pulled low if the output
voltage is outside the Power Good window.
© 2004 Semtech Corp.
7
www.semtech.com

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