SI3000PPT-EVB 데이터 시트보기 (PDF) - Silicon Laboratories

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SI3000PPT-EVB

EVALUATION BOARD FOR THE Si3000 WITH THE PARALLEL PORT INTERFACE

Silicon Laboratories 

Si3000PPT-EVB

If the system software chooses to allow the Si30xx EVB

to go off hook, the handset is excluded from the phone

loop and is connected directly to the Si3000 EVB. Voice

traffic is handled by the Si3000 and system software is

responsible for creating a virtual voice connection

between the handset and the phone system through the

Si3000 and Si30xx devices.

Microphone Interface

A standard 3.5 mm mini-phono connector located on

the daughter card connector J2 is used to provide an

interface from an external microphone to the Si3000.

The input impedance to MIC input of the Si3000 is at

least 10 kW. The Si3000 has a programmable pre-

amplification to support many input line levels.

If Jumper JP3 on the daughter card is populated, the

microphone can be powered directly from the Si3000

MBIAS output. The MBIAS output provides a typical

voltage of 2.5 V and can supply up to 5 mA,

programmable through an external resistor. For

applications that cannot be met by the Si3000’s MBIAS

output, the jumper may be removed and an external

biasing voltage can be applied to the microphone.

Speaker Interface

A standard 3.5 mm mini-phone connector is located on

the daughter card connector J3. The Si3000 SPKRR

and SPKRL outputs are designed to drive 60 W loads

directly. To drive a 32 W headset, an external series

resistor (30 W) is needed. Driving a 32 W headset

directly may result in reduced THD and Dynamic Range

performance. The maximum voltage swing is 1 Vrms for

either the left or right speaker drivers. The Si3000

speaker outputs have programmable analog

attenuation.

Line Input Interface

A standard RCA jack on the daughter card connector J5

is used to provide the line-level audio inputs to the

Si3000. The Si3000 has a programmable pre-amplifier.

The input impedance of the LINEI is at least 10 k. The

Si3000 supports multiple levels of pre-amplification to

support various line-levels.

Line Output Interface

A standard RCA jack on the daughter card connector J4

is used to provide the line-level audio outputs from the

Si3000. The Si3000 line output gain is programmable.

The maximum output voltage is 1 Vrms.

PC Parallel Port

JP13 connects through the Silicon Labs custom ribbon

cable to the parallel port of the PC. The parallel port

connection allows the designer to read and write the

Si3000 register using the evaluation software included

with the Si3000PPT-EVB.

Configuring the Si3000PPT-EVB

The S3000PPT-EVB is used to interface the Si3000

audio codec to a PC or other audio system for easy

evaluation. It uses an FPGA to translate the parallel port

interface to the SSI bus to communicate to the Si3000.

The audio data and control data are communicated from

the controlling PC using the aforementioned software.

This mode allows the user to evaluate the Si3000

without any lab equipment other than a PC.

When in mode 0, the negative edge of FSYNC indicates

the starting of the frame, and FSYNC is low until the end

of data transfer. By selecting mode 1 operation, the

rising edge of FSYNC indicates the start of the frame

but is only high for one cycle. To evaluate the Si3000’s

multiple device operation, chain the slave boards with

JP3 and JP4 on the moterboard to set to Mode 2. See

Table 1 for a description of these operating modes.

Table 1. Mode Configuration

Mode M1 M2

Description

0

0

0

FSYNC frames data

1

0

1 FSYNC pulse starts data frame

2

1

0

Slave mode

3

1

1

Reserved

The evaluation board has the ability to interface in two

different modes of the SSI bus: 5-bit address space

operation is used for the Si3000/34/35/44, and 7-bit

address space operation is used for the Si3056. The on-

board FPGA will auto-detect the chip and set the

appropreate registers.

Rev. 0.1

3

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