UT62257CLS-35L 데이터 시트보기 (PDF) - Utron Technology Inc

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UT62257CLS-35L

32K X 8 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



Rev. 1.1

UTRON

UT62257C

32K X 8 BIT LOW POWER CMOS SRAM

Notes :

1. WE , CE must be high or CE2 must be low during all address transitions.

2.A write occurs during the overlap of a low CE , high CE2, low WE .

3. During a WE controlled write cycle, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the

bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high

impedance state.

6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃)

PARAMETER

Vcc for Data Retention

Data Retention Current

Chip Disable to Data

Retention Time

Recovery Time

tRC* = Read Cycle Time

SYMBOL TEST CONDITION

VDR

CE ≧VCC-0.2V

or CE2 ≤ 0.2V

IDR

Vcc=3V, CE2 ≤ 0.2V

or CE ≧VCC-0.2V

tCDR See Data Retention

Waveforms (below)

tR

DATA RETENTION WAVEFORM

MIN.

2.0

-L

-

- LL -

0

tRC*

TYP.

-

MAX.

5.5

UNIT

V

1

50

µA

0.5

20

µA

-

-

ns

-

-

ns

Low Vcc Data Retention Waveform (1) ( CE controlled)

VCC

CE

Vcc(min.)

tCDR

VIH

VDR ≧ 2V

CE ≧ VCC-0.2V

Vcc(min.)

tR

VIH

Low Vcc Data Retention Waveform (2) (CE2 controlled)

VCC

CE2

VCC(min.)

tCDR

VIL

VDR ≧ 2V

CE2 ≦ 0.2V

VCC(min.)

tR

VIL

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

7

P80062

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