UT62257CSC-70LL(2001) 데이터 시트보기 (PDF) - Utron Technology Inc
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UT62257CSC-70LL Datasheet PDF : 12 Pages
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Rev. 1.0
UTRON
UT62257C
32K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
t WC
Address
CE1
CE2
t AS
WE
t AW
t CW1
t CW2
t WP
t WR
Dout
Din
t WH
(4)
High-Z
t DW
t OW
(4)
t DH
Data Valid
WRITE CYCLE 2 ( CE1 and CE2 Controlled) (1,2,5)
t WC
Address
CE1
t AS
CE2
t AW
t CW1
t CW2
t WR
WE
t WP
Dout
t WHZ
High-Z
t DW
t DH
Din
Data Valid
Notes :
1. WE or CE1 must be high and CE2 must be low during all address transitions.
2. A write occurs during the overlap of a low CE1 and a low WE ,and a high CE2.
3. During a WE controlled with write cycle, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to
be placed on the bus.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs or CE2 high simultaneously with or after WE LOW transition, the outputs remain in a
high impedance state.
6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
P80062
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