74LCX16652CW 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74LCX16652CW

Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs

Fairchild Semiconductor 

Functional Description

In the transceiver mode, data present at the HIGH imped-

ance port may be stored in either the A or B register or

both.

The select (SABn, SBAn) controls can multiplex stored and

real-time.

The examples below demonstrate the four fundamental

bus-management functions that can be performed with the

74LCX16652.

Data on the A or B data bus, or both can be stored in the

internal D flip-flop by LOW-to-HIGH transitions at the

appropriate Clock Inputs (CPABn, CPBAn) regardless of

the Select or Output Enable Inputs. When SAB and SBA

are in the real time transfer mode, it is also possible to

store data without using the internal D flip-flops by simulta-

neously enabling OEABn and OEBAn. In this configuration

each Output reinforces its Input. Thus when all other data

sources to the two sets of bus lines are in a HIGH imped-

ance state, each set of bus lines will remain at its last state.

Real-Time

Transfer Bus B to Bus A

Real-Time

Transfer Bus A to Bus B

OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1

L

L

X

X

XL

Transfer Storage

Data to A or B

OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1

H

H

X

X

LX

Storage

OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1

H

L H or L H or L H H

OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1

 X

H

X

XX

 L

X

X

XX

  L

H

XX

3

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