MAX186ACAP 데이터 시트보기 (PDF) - Maxim Integrated

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MAX186ACAP

Low-Power, 8-Channel, Serial 12-Bit ADCs

Maxim Integrated 

Low-Power, 8-Channel,

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise

noted.)

PARAMETER

Positive Supply Rejection

(Note 8)

Negative Supply Rejection

(Note 8)

SYMBOL

CONDITIONS

PSR

VDD = 5V ±5%; external reference, 4.096V;

full-scale input

PSR

VSS = -5V ±5%; external reference, 4.096V;

full-scale input

MIN TYP

±0.06

MAX

±0.5

±0.01 ±0.5

UNITS

mV

mV

Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.

Note 4: Ground on-channel; sine wave applied to all off channels.

Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.

Note 6: Guaranteed by design. Not subject to production testing.

Note 7: External load should not change during conversion for specified accuracy.

Note 8: Measured at VSUPPLY +5% and VSUPPLY -5% only.

Note 9: The common-mode range for the analog inputs is from VSS to VDD.

TIMING CHARACTERISTICS

(VDD = 5V ±5%; VSS =0V or -5V, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

Acquisition Time

tAZ

DIN to SCLK Setup

tDS

DIN to SCLK Hold

tDH

SCLK Fall to Output Data Valid

tDO

CS Fall to Output Enable

CS Rise to Output Disable

CS to SCLK Rise Setup

CS to SCLK Rise Hold

SCLK Pulse Width High

SCLK Pulse Width Low

SCLK Fall to SSTRB

CS Fall to SSTRB Output Enable

(Note 6)

CS Rise to SSTRB Output Disable

(Note 6)

SSTRB Rise to SCLK Rise

(Note 6)

tDV

tTR

tCSS

tCSH

tCH

tCL

tSSTRB

tSDV

tSTR

tSCK

CLOAD = 100pF

CLOAD = 100pF

CLOAD = 100pF

MAX18_ _C/E

MAX18_ _M

CLOAD = 100pF

External clock mode only, CLOAD = 100pF

External clock mode only, CLOAD = 100pF

Internal clock mode only

MIN

1.5

100

20

20

100

0

200

200

0

TYP

MAX

0

150

200

100

100

200

200

200

UNITS

µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

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