GS1582 데이터 시트보기 (PDF) - Semtech Corporation

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GS1582

Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

Semtech Corporation 

Table 1-1: Pin Descriptions (Continued)

Pin

Number

G6

G7

G8

Name

Timing

Type Description

SMPTE_BYPASS

IOPROC_EN/DIS

RESET

Non

Synchronous

Non

Synchronous

Non

Synchronous

Input

Input

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to enable/disable all forms of encoding/decoding, scrambling

and EDH insertion.

When set LOW, the device will operate in data through mode

(DVB_ASI = LOW), or in DVB-ASI mode (DVB_ASI = HIGH).

No SMPTE scrambling will take place and none of the I/O processing

features of the device will be available when SMPTE_BYPASS is set

LOW.

When set HIGH, the device will perform SMPTE scrambling and I/O

processing.

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to enable or disable I/O processing features.

When set HIGH, the following I/O processing features of the device

are enabled:

• Audio Embedding

• EDH Packet Generation and Insertion (SD-only)

• SMPTE 352M Packet Generation and Insertion

• ANC Data Checksum Calculation

• ANC Data Insertion

• Line-based CRC Generation and Insertion (HD-only)

• Line Number Generation and Insertion (HD-only)

• TRS Generation and Insertion

• Illegal Code Remapping

To enable a subset of these features, set IOPROC_EN/DIS = HIGH and

disable the individual feature(s) in the IOPROC_DISABLE register

accessible via the host interface.

When set LOW, the I/O processing features of the device are

disabled, and can not be enabled by changing the settings in the

IOPROC_DISABLE register.

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to reset the internal operating conditions to default settings

and to reset the JTAG test sequence.

Normal Mode (JTAG/HOST = LOW)

When set LOW, all functional blocks will be set to default conditions

and all input and output signals become high impedance including

the serial digital outputs SDO and SDO.

When set HIGH, normal operation of the device resumes 10usec

after the low to high transition of the RESET signal.

JTAG Test Mode (JTAG/HOST = HIGH)

When set LOW, all functional blocks will be set to default and the

JTAG test sequence will be held in reset.

When set HIGH, normal operation of the JTAG test sequence

resumes.

GS1582 Multi-Rate Serializer with Cable Driver, Audio

Multiplexer and ClockCleanerTM

Data Sheet

40117 - 4

December 2011

15 of 115

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