ESDA5V3SC5 데이터 시트보기 (PDF) - STMicroelectronics
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ESDA5V3SC5 Datasheet PDF : 11 Pages
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Application information
ESDAxxSCx
Figure 7.
Relative variation of leakage
current versus junction
temperature (typical values)
IR[Tj] / IR[Tj=25°C]
500
100
ESDA14V2SC5/SC6
&
ESDA6V1SC5/SC6
ESDA17SC6
&
ESDA19SC6
ESDA25SC6
10
Figure 8.
Peak forward voltage drop versus
peak forward current
(typical values)
5.00
1.00
IFM(A)
ESDA5V3SC5/SC6
ESDA14V2SC5/SC6
&
ESDA6V1SC5/SC6
ESDA19SC6
ESDA17SC6
ESDA25SC6
0.10
1
25
Tj(°C)
50
75
ESDA5V3SC5/SC6
100
125
VFM(V)
Tj = 25°C
0.01
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Application information
2.1
Calculation of the clamping voltage use of the dynamic
resistance
The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB
designers need to calculate easily the clamping voltage VCL. This is why we give the
dynamic resistance in addition to the classical parameters. The voltage across the
protection cell can be calculated with the following formula:
VCL = VBR + Rd IPP
Where IPP is the peak current through the ESDA cell.
As the value of the dynamic resistance remains stable for a surge duration lower than 20 µs,
the 2.5 µs rectangular surge is well adapted. In addition both rise and fall times are
optimized to avoid any parasitic phenomenon during the measurement of Rd.
2.2
Dynamic resistance measurement
The short duration of the ESD has led us to prefer a more adapted test wave, as below
defined, to the classical 8/20µs and 10/1000 µs surges.
Figure 9.
2.5 µs duration measurement wave
I
Ipp
2µs
t
tp = 2.5µs
4/11
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