DRP3510A 데이터 시트보기 (PDF) - Micronas

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DRP3510A

Digital Radio Processor

Micronas 

DRP 3510A

ADVANCE INFORMATION

1.1. Main Features

– single power supply 5 V

– 44-pin PLCC plastic package

– on-chip crystal oscillator (18.432 MHz or 24.576 MHz)

and internal DCO

– general purpose parallel interface

– 1 serial input interface and 2 serial output interfaces

I2S (32 kHz and 48 kHz audio out)

– SP/DIF output interface (48 kHz)

– I2C control interface

– download feature for alternative operation modes

1.2. Building Blocks

– 20-bit MASC DSP kernel

– 2-kWord internal RAM and 6-kWord ROM

(0.75 k config RAM)

– QPSK demodulator

– Viterbi decoder

– V.35 descrambling

– DMX-descrambler

– MPEG1 layer 2 decoder

– ancillary data processing

– sample rate converter

2. Functional Description

The incoming preprocessed ADR-data stream first

passes the carrier offset adjustment and the intersymbol

interference filtering blocks. Then, the sample rate of the

signal will be decimated to the symbol rate. A bit slicer

is used for the generation of the timing recovery and car-

rier offset adjustment control signals. Then, the signal is

sent to the soft decision viterbi decoder. A linear trans-

formation that is placed in front of the viterbi decoder

leads to an optimal signal mapping with respect to signal

space of the viterbi decoder. The output of the viterbi de-

coder is copied to the bit stream buffer of the following

MPEG1 layer 2 (MUSICAM) decoder.

After the data decompression, the audio signal is avail-

able at a sampling frequency of 48 kHz at the I2S and the

SP/DIF output interfaces. A third output is used as audio

feedback for the MSP. For compatibility reasons, a sam-

ple rate converter reduces the sampling frequency to 32

kHz. In addition to the pure audio signal, some ancillary

data are embedded in the MPEG signal. These data are

extracted, deinterleaved, error corrected, and sent to the

I2C interface, where they may be read by the receiver

system controller. The software/hardware module that

performs a descrambling of pay radio services (in addi-

tion to a verifier IC and a “smart card” reader) is also con-

trolled via the I2C bus.

ADRIN

3

ADR(1)

Channel

Demod-

ulation

DMX

ADR-Data

2

Control

PIO

I2C

Fig. 1–2: DRP 3510A simplified block diagram

6

Output

Clock

Control

Musicam

Decoder

1

48 kHz

AUDIO

SP/DIF

3

48 kHz

AUDIO

I2S

SDO (0)

48↓32 kHz

3

32 kHz

AUDIO

I2S

SDO(1)

10

MPEG

PC

interface

Micronas

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