CXD2720Q 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2720Q

Single-Chip Digital Signal Processor for Karaoke

Sony Semiconductor 

CXD2720Q

Item

Symbol

RVDT setup time relative to SCK rise

tDS

RVDT data hold time from SCK rise

tDH

SCK Low level width

tSWL

SCK High level width

tSWH

XLAT Low level width

tLWL

XLAT High level width

tLWH

SCK rise preceding time relative to XLAT rise

tSLP

SCK rise wait time relative to XLAT rise

tLSD

Delay time to REDY fall relative to XLAT rise.

tLBD

Delay time to REDY fall relative to SCK rise

tSBD

REDY fall preceding time relative to SCK rise

tBSP

REDY rise preceding time relative to XLAT rise

tRLP

REDY rise preceding time relative to SCK fall

tRSDP

XLAT fall wait time relative to SCK rise

tSLD

XLAT fall delay time relative to REDY fall

tLDR

Delay time from XLAT rise until TRDT data becomes active

tLDN

Delay time from SCK rise until TRDT data becomes high-impedance tSDF

Delay time from SCK fall until TRDT data is verified

tSDD

CK rise wait time for next transmission

tSS

Note 1) t is the cycle of 1/2 the clock frequency applied to the XTLI pin. (384fs)

Note 2) REDY and TRDT pins are the values for CL = 60pF.

Min.

20

1t + 20

1t + 20

1t + 20

1t + 20

1t + 20

20

3t + 20

20

20

20

3t + 20

20

2t + 40

Max. Unit

ns

ns

ns

ns

ns

ns

ns

ns

3t + 50 ns

4t + 50 ns

ns

ns

ns

ns

ns

3t + 80 ns

3t + 80 ns

2t + 70 ns

ns

–8–

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