HMP8154 데이터 시트보기 (PDF) - Renesas Electronics
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HMP8154 Datasheet PDF : 34 Pages
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HMP8154, HMP8156A
16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats
with Flicker Filtering
When the 16-bit YCbCr, 16-bit RGB, or 24-bit RGB data
format is selected and flicker filtering is enabled, pixel and
overlay data is latched on every rising edge of CLK2. The
pixel and overlay input timing is shown in Figures 9-11.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency.
CLK2
P8-P15
P0-P7
OL0-OL2,
M1, M0
BLANK
(INPUT)
BLANK
(OUTPUT)
Y0
Y1
Y2
Y3
Y4
Y5
Cb 0
Cr 0
Cb 2
Cr 2
Cb 4
Cr 4
PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5
YN
Cr N-1
PIXEL N
FIGURE 9. PIXEL AND OVERLAY INPUT TIMING - 16-BIT YCBCR WITH FLICKER FILTERING
CLK2
P0-P15
OL0-OL2,
M1, M0
BLANK
(INPUT)
BLANK
(OUTPUT)
RGB 0
RGB 1
RGB 2
RGB 3
RGB 4
RGB 5
PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5
RGB N
PIXEL N
FIGURE 10. PIXEL AND OVERLAY INPUT TIMING - 16-BIT RGB WITH FLICKER FILTERING
CLK2
P0-P23
BLANK
(INPUT)
BLANK
(OUTPUT)
RGB 0
RGB 1
RGB 2
RGB 3
RGB 4
RGB 5
RGB N
FIGURE 11. PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITH FLICKER FILTERING
FN4343 Rev.5.00
August 20, 2009
Page 10 of 34
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