HI5762(1999) 데이터 시트보기 (PDF) - Intersil

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HI5762
(Rev.:1999)

Dual 10-Bit, 60MSPS A/D Converter with Internal Voltage Reference

Intersil 

HI5762

As illustrated in the functional block diagram and the timing

diagram in Figure 1, eight identical pipeline subconverter

stages, each containing a two-bit flash converter and a two-

bit multiplying digital-to-analog converter, follow the S/H

circuit with the ninth stage being a two bit flash converter.

Each converter stage in the pipeline will be sampling in one

phase and amplifying in the other clock phase. Each

individual subconverter clock signal is offset by 180 degrees

from the previous stage clock signal resulting in alternate

stages in the pipeline performing the same operation.

The output of each of the eight identical two-bit subconverter

stages is a two-bit digital word containing a supplementary bit

to be used by the digital error correction logic. The output of

each subconverter stage is input to a digital delay line which is

controlled by the internal sampling clock. The function of the

digital delay line is to time align the digital outputs of the eight

identical two-bit subconverter stages with the corresponding

output of the ninth stage flash converter before applying the

eighteen bit result to the digital error correction logic. The

digital error correction logic uses the supplementary bits to

correct any error that may exist before generating the final ten

bit digital data output of the converter.

Because of the pipeline nature of this converter, the digital

data representing an analog input sample is output to the

digital data bus following the 6th cycle of the clock after the

analog sample is taken (see the timing diagram in Figure 1).

This time delay is specified as the data latency. After the

data latency time, the digital data representing each

succeeding analog sample is output during the following

clock cycle. The digital output data is provided in offset

binary format (see Table 1, A/D Code Table).

Internal Reference Voltage Output, VREFOUT

The HI5762 is equipped with an internal reference voltage

generator, therefore, no external reference voltage is

required. VROUT must be connected to VRIN when using the

internal reference voltage.

An internal band-gap reference voltage followed by an

amplifier/buffer generates the precision +2.5V reference voltage

used by the converter. A band-gap reference circuit is used to

generate a precision +1.25V internal reference voltage. This

voltage is then amplified by a wide-band uncompensated

operational amplifier connected in a gain-of-two configuration.

An external, user-supplied, 0.1µF capacitor connected from the

VROUT output pin to analog ground is used to set the dominant

pole and to maintain the stability of the operational amplifier.

Reference Voltage Input, VREFIN

The HI5762 is designed to accept a +2.5V reference voltage

source at the VRIN input pin. Typical operation of the

converter requires VRIN to be set at +2.5V. The HI5762 is

tested with VRIN connected to VROUT yielding a fully

differential analog input voltage range of ±0.5V.

The user does have the option of supplying an external +2.5V

reference voltage. As a result of the high input impedance

presented at the VRIN input pin, 1.25kΩ typically, the external

reference voltage being used is only required to source 2mA

of reference input current. In the situation where an external

reference voltage will be used an external 0.1µF capacitor

must be connected from the VROUT output pin to analog

ground in order to maintain the stability of the internal

operational amplifier.

In order to minimize overall converter noise it is

recommended that adequate high frequency decoupling be

provided at the reference voltage input pin, VRIN .

Analog Input, Differential Connection

The analog input of the HI5762 is a differential input that can

be configured in various ways depending on the signal

source and the required level of performance. A fully

differential connection (Figure 16 and Figure 17) will deliver

the best performance from the converter.

VIN

-VIN

I/QIN+

R

HI5762

I/QVDC

R

I/QIN-

FIGURE 16. AC COUPLED DIFFERENTIAL INPUT

Since the HI5762 is powered by a single +5V analog supply,

the analog input is limited to be between ground and +5V.

For the differential input connection this implies the analog

input common mode voltage can range from 0.25V to 4.75V.

The performance of the ADC does not change significantly

with the value of the analog input common mode voltage.

A DC voltage source, I/QVDC, equal to 3.0V (typical), is

made available to the user to help simplify circuit design

when using an AC coupled differential input. This low output

impedance voltage source is not designed to be a reference

but makes an excellent DC bias source and stays well within

the analog input common mode voltage range over

temperature.

For the AC coupled differential input (Figure 16) and with VRIN

connected to VROUT, full scale is achieved when the VIN and

-VIN input signals are 0.5VP-P, with -VIN being 180 degrees

out of phase with VIN. The converter will be at positive full

scale when the I/QIN+ input is at VDC + 0.25V and the I/QIN-

input is at VDC - 0.25V (I/QIN+ - I/QIN- = +0.5V). Conversely,

the converter will be at negative full scale when the I/QIN+

input is equal to VDC - 0.25V and I/QIN- is at

VDC + 0.25V (I/QIN+ - I/QIN- = -0.5V).

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