ACTS373D/SAMPLE 데이터 시트보기 (PDF) - Intersil

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ACTS373D/SAMPLE

Radiation Hardened Octal Transparent Latch, Three-State

Intersil 

Specifications ACTS373MS

Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger and AC Load Circuit

INPUT

VIH

VIL

INPUT CP

VIH

VIL

VS

TSU

VS

TH = HOLD TIME

TSU = SETUP TIME

TW = PULSE WIDTH

TW

TH

TW

DUT

CL

50pF

TEST

POINT

RL

500Ω

PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS

PARAMETER

VCC

VIH

VS

VIL

GND

ACTS

4.50

3.00

1.30

0

0

UNITS

V

V

V

V

V

Three-State High Timing Diagram and Load Circuit

VIH

VS

VSS

VOH

VOZ

INPUT

TPZH

VT

TPHZ

OUTPUT

VW

DUT

CL

50pF

TEST

POINT

RL

500Ω

PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS

PARAMETER

VCC

VIH

VS

VT

VW

GND

ACTS

4.50

3.00

1.30

1.30

3.60

0

UNITS

V

V

V

V

V

V

Three-State Low Timing Diagram and Load Circuit

VIH

VS

INPUT

VSS

VOZ

TPZL

TPLZ

VT

OUTPUT

VW

VOL

DUT

VCC

RL

500Ω

CL

50pF

TEST

POINT

PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS

PARAMETER

VCC

VIH

VS

VT

VW

GND

ACTS

4.50

3.00

1.30

1.30

0.90

0

UNITS

V

V

V

V

V

V

Spec Number 518800

7

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