PD45128163G5-A10LI-9JF 데이터 시트보기 (PDF) - Elpida Memory, Inc

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PD45128163G5-A10LI-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Elpida Memory, Inc 

µPD45128441-I, 45128841-I, 45128163-I

6. Programming the Mode Register

The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0(A13)

and BA1(A12) as data inputs. The register retains data until it is reprogrammed or the device loses power.

The mode register has four fields;

Options

: A11 through A7, BA0(A13), BA1(A12)

/CAS latency : A6 through A4

Wrap type : A3

Burst length : A2 through A0

Following mode register programming, no command can be issued before at least 2 CLK have elapsed.

/CAS Latency

/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse

before the data will be available.

The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship

between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of

the device.

Burst Length

Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is

completed, the output bus will become Hi-Z.

The burst length is programmable as 1, 2, 4, 8 or full page.

Wrap Type (Burst Sequence)

The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either

“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.

Some microprocessor cache systems are optimized for sequential addressing and others for interleaved

addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them.

Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.

Preliminary Data Sheet E0233N10

21

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