UL634H256BSC55 데이터 시트보기 (PDF) - Zentrum Mikroelektronik Dresden AG
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UL634H256BSC55 Datasheet PDF : 13 Pages
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UL635H256
PowerStore and automatic Power Up RECALL
VCC
3.0 V
VSWITCH
PowerStore
Power Up
RECALL
W
DQi
(24)
tRESTORE
tPDSTOREp
t
(24)
tRESTORE
tDELAYp
POWER UP BROWN OUT
BROWN OUT
RECALL NO STORE
PowerStore
(NO SRAM WRITES)
No.
Software Controlled STORE/RECALL
Cyclek, o
Symbol
Alt.
IEC
35
Min.
Max.
45
Min. Max.
Unit
27 STORE/RECALL Initiation Time
28 Chip Enable to Output Inactivep
29 STORE Cycle Timeq
30 RECALL Cycle Timer
31 Address Setup to Chip Enables
32 Chip Enable Pulse Widths, t
33 Chip Disable to Address Changes
tAVAV
tcR
35
45
ns
tELQZ
tdis(E)SR
600
600 ns
tELQXS
td(E)S
10
10
ms
tELQXR
td(E)R
20
20
µs
tAVELN
tsu(A)SR
0
0
ns
tELEHN
tw(E)SR
25
30
ns
tEHAXN
th(A)SR
0
0
ns
o: The software sequence is clocked with E controlled READs.
p: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
q: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
s: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
t: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
8
April 7, 2005
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