UL634H256BTC55 데이터 시트보기 (PDF) - Zentrum Mikroelektronik Dresden AG
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UL634H256BTC55 Datasheet PDF : 13 Pages
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UL635H256
Nonvolatile Memory Operations
Mode Selection
E
W
A13 - A0
(hex)
Mode
I/O
H
X
X
Not Selected
Output High Z
L
H
X
L
L
X
Read SRAM
Write SRAM
Output Data
Input Data
L
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Standby
Active
Active
Active
Active
Notes
m
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: While there are 15 addresses on the UL635H256, only the lower 14 are used to control software modes.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G ≤ VIL.
PowerStore
No. Power Up RECALL
24 Power Up RECALL Durationn
25 STORE Cycle Durationf, e
26
Time allowed to Complete SRAM
Cyclef
Low Voltage Trigger Level
Symbol
Alt.
IEC
tRESTORE
tPDSTORE
Conditions
Min. Max. Unit
the power supply decay
rate has to be smaller
than 10 Vs-1 after the
start of the STORE
operation
650 µs
10 ms
tDELAY
VSWITCH
500
ns
2.4 2.7 V
n: tRESTORE starts from the time VCC rises above VSWITCH.
April 7, 2005
7
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