HD74LV125ARPEL 데이터 시트보기 (PDF) - Renesas Electronics

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HD74LV125ARPEL

Quad. Bus Buffer Gates with 3-state Outputs

Renesas Electronics 

HD74LV125A

• Waveform − 1

Input A

tr

10 %

90 %

50 %VCC

tPLH

tf

90 %

50 %VCC

10 %

tPHL

Output Y

50 %VCC

50 %VCC

VCC

GND

VOH

VOL

• Waveform − 2

tf

90 %

Input OE 50 %VCC

10 %

tZL

Waveform − A

Waveform − B

50 %VCC

tZH

50 %VCC

tr

10 %

90 %

50 %VCC

tLZ

VOL + 0.3 V

tHZ

VOH − 0.3 V

VCC

GND

VCC

VOL

VOH

GND

Notes: 1. tr ≤ 3 ns, tf ≤ 3 ns

2. Input waveform: PRR ≤ 1 MHz, duty cycle 50%

3. Waveform−A is for an output with internal conditions such that the output is low except when

disabled by the output control.

4. Waveform−B is for an output with internal conditions such that the output is high except when

disabled by the output control.

Rev.3.00 Jun. 03, 2004 page 7 of 9

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