PDSP1601A 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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PDSP1601A Datasheet PDF : 16 Pages
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PDSP1601/PDSP1601A
The Register Files
There are two on-chip register files (ALU and Shifter), each
containing two 16 bit registers and each supporting 8
instructions (see Table 4). The instructions for the ALU
register file and the Barrel Shifter Register file are the same.
The Inputs to the register files come from either the ALU or
the Barrel Shifter, and are loaded into the Register files on the
rising edge of CLK.
The register file instructions are latched such that the
instruction will not start executing until the rising edge of the
CLK latches the instruction into the device.
The register file instructions (see Table 4) allow input data
to be loaded into either, neither or both of the registers. Data
is loaded at the end of the cycle in which the instruction is
executing.
The register file instructions allow the output to be sourced
from either of the two registers, the selected output will be valid
during the cycle in which the instruction is executing.
ALU REGISTER INSTRUCTIONS
Inst RA2-RA0 Mnemonic
Operation
0
000
LLRRR Load Left Reg Output Right Reg
1
001
LRRLR Load Right Reg Output Left Reg
2
010
LLRLR Load Left Register, Output Left Reg
3
011
LRRRR Load Right Register, Output Right Reg
4
100
LBRLR Load Both Registers, Output Left Reg
5
101
NOPRR No Load Operation, Output Right Reg
6
110
NOPLR No Load Operation, Output Left Reg
7
111
NOPPS No Load Operation, Pass ALU Result
SHIFTER REGISTER INSTRUCTIONS
Inst RA2-RA0 Mnemonic
Operation
0
000
LLRRR Load Left Reg Output Right Reg
1
001
LRRLR Load Right Reg Output Left Reg
2
010
LLRLR Load Left Register, Output Left Reg
3
011
LRRRR Load Right Register, Output Right Reg
4
100
LBRLR Load Both Registers, Output Left Reg
5
101
NOPRR No Load Operation, Output Right Reg
6
110
NOPLR No Load Operation, Output Left Reg
7
111
NOPPS No Load Operation, Pass Barrel Shifter Result
Table 4 ALU and shift register instructions mnemonics
MNEMONICS
LXXYY Load XX = Target, YY
LBOXX Load Both Registers, XX
NOPXX No Load Operation, XX
= Source of Output
= Source of Output
= Source of Output
8
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