84052IVZ 데이터 시트보기 (PDF) - Renesas Electronics

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84052IVZ

Low Voltage, Single and Dual Supply, 8-to-1 Multiplexer, Dual 4-to-1 Multiplexer and a Triple SPDT Analog Switch

Renesas Electronics 

ISL84051, ISL84052, ISL84053

Package Outline Drawing

M16.173

16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 2, 5/10

A

13

5.00 ±0.10

16

9

6.40

4.40 ±0.10

2

3

PIN #1

I.D. MARK

0.20 C B A 1

8

0.65

B

TOP VIEW

SEE DETAIL "X"

0.09-0.20

END VIEW

H

C

SEATING

PLANE

0.10 C

- 0.05

1.20 MAX

0.90 +0.15/-0.10

0.25 +0.05/-0.06 5

0.10 M C B A

SIDE VIEW

0.05 MIN

0.15 MAX

1.00 REF

GAUGE

PLANE

0.25

DETAIL "X"

0°-8°

0.60 ±0.15

(5.65)

(1.45)

(0.65 TYP)

(0.35 TYP)

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

3. Dimensions are measured at datum plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.08mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead

is 0.07mm.

6. Dimension in ( ) are for reference only.

7. Conforms to JEDEC MO-153.

FN6047 Rev.10.00

May 16, 2011

Page 18 of 19

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