CY7C132(2005) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C132
(Rev.:2005)

2K x 8 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Busy Timing Diagram No. 1 (CE Arbitration)

CEL Valid First:

ADDRESSL,R

ADDRESS MATCH

CEL

CER

BUSYR

CER Valid First:

tPS

tBLC

tBHC

ADDRESSL,R

ADDRESS MATCH

CER

CEL

BUSYL

tPS

tBLC

tBHC

Busy Timing Diagram No. 2 (Address Arbitration)

Left Address Valid First:

ADDRESSL

ADDRESSR

BUSYR

Right Address Valid First:

tRC or tWC

ADDRESS MATCH

tPS

tBLA

ADDRESSR

ADDRESSL

tRC or tWC

ADDRESS MATCH

tPS

tBLA

BUSYL

ADDRESS MISMATCH

tBHA

ADDRESS MISMATCH

tBHA

CY7C132/CY7C136

CY7C142/CY7C146

Document #: 38-06031 Rev. *C

Page 9 of 18

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