CY7C132(2005) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C132 Datasheet PDF : 18 Pages
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CY7C132/CY7C136
CY7C142/CY7C146
Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) (continued)[5, 10]
7C136-15[3]
7C146-15
7C132-25[3]
7C136-25
7C142-25
7C146-25
7C132-30
7C136-30
7C142-30
7C146-30
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
Busy/Interrupt Timing
tBLA
BUSY LOW from Address Match
tBHA
BUSY HIGH from Address Mismatch[15]
tBLC
tBHC
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[15]
tPS
Port Set Up for Priority
tWB
R/W LOW after BUSY LOW[16]
tWH
R/W HIGH after BUSY HIGH
tBDD
BUSY HIGH to Valid Data
tDDD
Write Data Valid to Read Data Valid
tWDD
Write Pulse to Data Delay
Interrupt Timing[18]
15
20
20
ns
15
20
20
ns
15
20
20
ns
15
20
20
ns
5
5
5
ns
0
0
0
ns
13
20
30
ns
15
25
30
ns
Note 17
Note 17
Note 17 ns
Note 17
Note 17
Note 17 ns
tWINS
R/W to INTERRUPT Set Time
15
25
tEINS
CE to INTERRUPT Set Time
15
25
tINS
Address to INTERRUPT Set Time
15
25
tOINR
OE to INTERRUPT Reset Time[15]
15
25
tEINR
CE to INTERRUPT Reset Time[15]
15
25
tINR
Address to INTERRUPT Reset Time[15]
15
25
Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) [5, 10]
25
ns
25
ns
25
ns
25
ns
25
ns
25
ns
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid[11]
35
45
55
ns
35
45
55
ns
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
Data Hold from Address Change
CE LOW to Data Valid[11]
OE LOW to Data Valid[11]
OE LOW to Low Z[9, 12]
OE HIGH to High Z[9, 12, 13]
CE LOW to Low Z[9, 12]
CE HIGH to High Z[9, 12, 13]
CE LOW to Power-Up[9]
CE HIGH to Power-Down[9]
0
0
0
ns
35
45
55
ns
20
25
25
ns
3
3
3
ns
20
20
25
ns
5
5
5
ns
20
20
25
ns
0
0
0
ns
35
35
35
ns
Notes:
15. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
16. CY7C142/CY7C146 only.
17. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
18. 52-pin PLCC and PQFP versions only.
Document #: 38-06031 Rev. *C
Page 5 of 18
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