AK4550 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AK4550

Low Power & Small Package 16bit ∆Σ CODEC

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4550]

n Power-down & Reset

The ADC and DAC of AK4550 are placed in the power-down mode by bringing each power down pin, PWAD , PWDA

= “L” independently and each digital filter is also reset at the same time. These resets should always be done after

power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the

output data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC

operation. Figure 2 shows the power-up sequence when the ADC is powered up before the DAC power-up.

PWAD

ADC Internal

State

PWDA

DAC Internal

State

ADC In

(Analog)

ADC Out

(Digital)

DAC In

(Digital)

DAC Out

(Analog)

Clock In

MCLK,LRCK,SCLK

External

Mute

Normal Operation

Power-down

2081/fs

Init Cycle

Normal Operation

Normal Operation

Power-down

Normal Operation

GD

GD

Idle Noise

GD

“0”data

“0”data

Idle Noise

GD

The clocks may be stopped.

Mute ON

Figure 2. Power-up Sequence

M0068-E-01

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