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s BLOCK DIAGRAM
MB91107/108
FR CPU
I-bus
Instruction Cache
1 KB
Bit Search Module
DMAC (8 ch)
DREQ0 DREQ1 DREQ2
DACK0 DACK1 DACK2
EOP0 EOP1 EOP2
(16 bit)
D-bus (32 bit)
32 bit
16 bit
Bus Converter
X0 X1
RST
HST
Clock Control Unit
(Watch Dog Timer)
INT0 ∼ INT7
NMI
Interrupt Control Unit
AN0 ∼ AN3
AVCC AVRH
AVSS AVRL
ATG
10 bit A/D
Converter (4 ch)
Reload Timer (3 ch)
R-bus (16 bit)
Port
Harvard
Princeton
Bus Converter
Bus Controller
D31 ∼ D16
A24 ∼ A00
RD
WR0 ∼ WR1
RDY
CLK
CS0 ∼ CS7
BRQ BGRNT
C-bus
RAM 128 KB (MB91107)
RAM 160 KB (MB91108)
DRAM Controller
RAS0 RAS1
CS0L CS1L
CS0H CS1H
DW0 DW1
(32 bit)
Port 0 ∼ Port B
UART (3 ch)
with
Baud Rate Timer
SI0 SI1 SI2
SO0 SO1 SO2
SC0 SC1 SC2
PWM Timer (4 ch)
OCPA0 ∼ OCPA3
TRG0 ∼ TRG3
Note: Pins are display for functions (Actually some pins are multiplexer).
When using REALOS, time control should be done by using external interrupt or inner timer.
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