LC72144M 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LC72144M Datasheet PDF : 22 Pages
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LC72144M
Control Data Functions
Control section/
No. data
Function
Data that sets the programmable divider’s divisor. It is a binary value and P15 is the MSB. The LSB
differs depending on the DVS and SNS bits. (!: don’t care)
DVS
SNS
LSB
Divisor setting (N)
1
!
P0
272 to 65535
0
1
P0
272 to 65535
Programmable
0
0
P4
4 to 4095
divider data Note: When P4 is the LSB, P0 to P3 are ignored.
(1)
P0 to P15, These bits select the signal input pin (FMIN or AMIN) for the programmable divider and switch the input
DVS, SNS frequency range.
DVS
1
SNS
!
Input port
FMIN
Input frequency range (MHz)
10 to 160
0
1
AMIN
2 to 40
0
0
AMIN
0.5 to 10
Note: See the “Programmable Divider Structure” item for details.
Data that controls the sub-change pump
PDC1
PDC0
Sub-charge pump state
Sub-charge
0
!
High impedance
pump
(2)
control data
1
0
Charge pump operates (when unlocked)
1
1
Charge pump operates (normal operation)
PDC0, PDC1
Note: The sub-charge pump can form a high-speed lockup circuit when combined with the PD0 and
PD1 pins (the main charge pump).
See the item on the structure of the charge pump for details.
Data that selects the reference frequency (fref)
R3
R2
R1
R0
Reference frequency (kHz)
0
0
0
0
100*1
0
0
0
1
50
0
0
1
0
25
0
0
1
1
25
0
1
0
0
12.5
0
1
0
1
6.25
0
1
1
0
3.125
0
1
1
1
Reference
(3) divider data
1
0
0
0
R0 to R3
1
0
0
1
1
0
1
0
3.125
10
9*2
5
1
0
1
1
1
1
1
0
0
3*2
1
1
0
1
30*2
1
1
1
0
*3, PLL inhibited and crystal oscillator stopped
1
1
1
1
*3, PLL inhibited
Note: 1. Cannot be used when the crystal oscillator frequency is 10.25 or 10.35 MHz.
Note: 2. Cannot be used when the crystal oscillator frequency is 10.25 MHz.
Note: 3. PLL inhibit (backup mode)
The programmable divider block is stopped and FMIN and AMIN are both pulled down to
ground. The charge pump output goes to the floating state.
Related data
UL0, UL1, DLC
Continued on next page.
No. 5377-10/22
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