MAX9867 데이터 시트보기 (PDF) - Maxim Integrated
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MAX9867 Datasheet PDF : 55 Pages
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Ultra-Low Power Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN in differential
mode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =
0dB, MCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
DIGITAL SIDETONE
Sidetone Gain Adjust Range
AVSTGA
Differential output mode,
DVST = 0x1F to 0x01
-60
Voice Path Phase Delay
PDLY
MIC input to headphone output, f = 1kHz,
HP filter disabled, fS = 8kHz
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency
fMCLK For any LRCLK sample rate
10
Prescaler = /1 mode
40
MCLK Input Duty Cycle
/2 or /4 modes
30
Maximum MCLK Input Jitter
LRCLK Sample Rate Range
LRCLK PLL Lock Time
Maximum allowable RMS for performance
limits
8
Any allowable LRCLK
and PCLK rate, slave
mode
Rapid lock mode
Nonrapid lock
mode
TYP MAX UNITS
0
dB
2.2
ms
60
MHz
60
%
70
100
psRMS
48
kHz
2
7
ms
12
25
LRCLK Acceptable Jitter for
Maintaining PLL Lock
LRCLK Average Frequency Error
(Master and Slave Modes)
(Note 9)
DIGITAL INPUT (MCLK)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage Current
Input Capacitance
IIH, IIL
DIGITAL INPUTS (SDIN, BCLK, LRCLK)
Input High Voltage
VIH
Allowable LRCLK period change from
nominal for slave PLL mode at any
allowable LRCLK and PCLK rates
FREQ = 0x8 through 0xF
PCLK = 192xfS, 256xfS, 384xfS, 512xfS,
768xfS, and 1024xfS
All other modes
TA = +25°C
Input Low Voltage
Input Hysteresis
Input Leakage Current
Input Capacitance
VIL
IIH, IIL TA = +25°C
±100
ns
0
0
-0.025
0
%
0
+0.025
1.2
V
0.6
V
±1
µA
10
pF
0.7 x
V
DVDDIO
0.3 x
DVDDIO
V
200
mV
±1
µA
10
pF
10 ______________________________________________________________________________________
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