7C1338-100 데이터 시트보기 (PDF) - Cypress Semiconductor
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7C1338-100 Datasheet PDF : 16 Pages
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CY7C1338
Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor’s Sequence
First
Address
AX + 1, Ax
00
01
10
11
Second
Address
AX + 1, Ax
01
00
11
10
Third
Address
AX + 1, Ax
10
11
00
01
Fourth
Address
AX + 1, Ax
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW. Leaving ZZ unconnected defaults the device into an ac-
tive state.
Table 2. Counter Implementation for a Linear Sequence
First
Address
AX + 1, Ax
00
01
10
11
Second
Address
AX + 1, Ax
01
10
11
00
Third
Address
AX + 1, Ax
10
11
00
01
Fourth
Address
AX + 1, Ax
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
ICCZZ
Snooze mode
standby current
ZZ > VDD − 0.2V
10
mA
tZZS
Device operation to ZZ > VDD − 0.2V
ZZ
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
5
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