CXA7000R 데이터 시트보기 (PDF) - Sony Semiconductor
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CXA7000R Datasheet PDF : 23 Pages
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CXA7000R
Pin
No.
Symbol
I/O
Standard
voltage level
48 SL_DAT
High: ≥2.0V
I Low: ≤0.8V
Open: Low
Equivalent circuit
VDD
48
GND
50k
192
200k
Description
Digital input mode switch setting.
High: when using master/slave
mode two CXA7000R.
Low: when using normal mode
one CXA7000R.
50 STATUS
I
High: ≥2.0V
Low: ≤0.8V
VDD
50
50k
200k
192
GND
Master/slave setting when using
two CXA7000R.
High: master IC. Offset cancel
level is output.
Low: slave IC. This pin is left
open (high) when using one
CXA7000R.
51
to
55 D_IN9 to
58 D_IN0
to
62
I
High: ≥2.0V
Low: ≤0.8V
VDD
50k
192
51 to 55
58 to 62
GND
Digital data input.
63 MCLK
64 MCLKX
VDD
PECL
differential
(amplitude
63
I 0.4V or more
between
64
VDD to 2V)
or TTL input
GND
140k
1k
1k
60k
8k 140k
Dot clock input.
PECL differential input or TTL
input. For TTL input, input to
MCLK and connect MCLKX to
GND through a capacitor.
100µ 60k
42 PS
I
5V
24, 25 PGND
17, 32 PVCC
35 VCC15
43 VDD5
GND
15.5V
15.5V
5V
VDD
70k
42
GND
180k
30µ
–6–
Test.
Normally connect to VDD.
Power GND.
Power VCC.
15V power supply.
5V power supply.
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